Periph ID AIC | Symbol | Description |
---|---|---|
27 | (AT91C_ID_DMA) | DMA Controller |
Function | Description |
---|---|
AT91F_DMA_CfgPMC | Enable Peripheral clock in PMC for DMA |
Offset | Field | Description |
---|---|---|
0x0 | DMA_SAR0 (DMA_SAR) | Source Address Register for channel 0 |
0x8 | DMA_DAR0 (DMA_DAR) | Destination Address Register for channel 0 |
0x10 | DMA_LLP0 (DMA_LLP) | Linked List Pointer Register for channel 0 |
0x18 | DMA_CTL0l (DMA_CTLl) | Control Register for channel 0 - low |
0x1C | DMA_CTL0h (DMA_CTLh) | Control Register for channel 0 - high |
0x20 | DMA_SSTAT0 (DMA_SSTAT) | Source Status Register for channel 0 |
0x28 | DMA_DSTAT0 (DMA_DSTAT) | Destination Status Register for channel 0 |
0x30 | DMA_SSTATAR0 (DMA_SSTATAR) | Source Status Adress Register for channel 0 |
0x38 | DMA_DSTATAR0 (DMA_DSTATAR) | Destination Status Adress Register for channel 0 |
0x40 | DMA_CFG0l (DMA_CFGl) | Configuration Register for channel 0 - low |
0x44 | DMA_CFG0h (DMA_CFGh) | Configuration Register for channel 0 - high |
0x48 | DMA_SGR0 (DMA_SGR) | Source Gather Register for channel 0 |
0x50 | DMA_DSR0 (DMA_DSR) | Destination Scatter Register for channel 0 |
0x58 | DMA_SAR1 (DMA_SAR) | Source Address Register for channel 1 |
0x60 | DMA_DAR1 (DMA_DAR) | Destination Address Register for channel 1 |
0x68 | DMA_LLP1 (DMA_LLP) | Linked List Pointer Register for channel 1 |
0x70 | DMA_CTL1l (DMA_CTLl) | Control Register for channel 1 - low |
0x74 | DMA_CTL1h (DMA_CTLh) | Control Register for channel 1 - high |
0x78 | DMA_SSTAT1 (DMA_SSTAT) | Source Status Register for channel 1 |
0x80 | DMA_DSTAT1 (DMA_DSTAT) | Destination Status Register for channel 1 |
0x88 | DMA_SSTATAR1 (DMA_SSTATAR) | Source Status Adress Register for channel 1 |
0x90 | DMA_DSTATAR1 (DMA_DSTATAR) | Destination Status Adress Register for channel 1 |
0x98 | DMA_CFG1l (DMA_CFGl) | Configuration Register for channel 1 - low |
0x9C | DMA_CFG1h (DMA_CFGh) | Configuration Register for channel 1 - high |
0xA0 | DMA_SGR1 (DMA_SGR) | Source Gather Register for channel 1 |
0xA8 | DMA_DSR1 (DMA_DSR) | Destination Scatter Register for channel 1 |
0x2C0 | DMA_RAWTFR | Raw Status for IntTfr Interrupt |
0x2C8 | DMA_RAWBLOCK | Raw Status for IntBlock Interrupt |
0x2D0 | DMA_RAWSRCTRAN | Raw Status for IntSrcTran Interrupt |
0x2D8 | DMA_RAWDSTTRAN | Raw Status for IntDstTran Interrupt |
0x2E0 | DMA_RAWERR | Raw Status for IntErr Interrupt |
0x2E8 | DMA_STATUSTFR | Status for IntTfr Interrupt |
0x2F0 | DMA_STATUSBLOCK | Status for IntBlock Interrupt |
0x2F8 | DMA_STATUSSRCTRAN | Status for IntSrcTran Interrupt |
0x300 | DMA_STATUSDSTTRAN | Status for IntDstTran IInterrupt |
0x308 | DMA_STATUSERR | Status for IntErr IInterrupt |
0x310 | DMA_MASKTFR | Mask for IntTfr Interrupt |
0x318 | DMA_MASKBLOCK | Mask for IntBlock Interrupt |
0x320 | DMA_MASKSRCTRAN | Mask for IntSrcTran Interrupt |
0x328 | DMA_MASKDSTTRAN | Mask for IntDstTran Interrupt |
0x330 | DMA_MASKERR | Mask for IntErr Interrupt |
0x338 | DMA_CLEARTFR | Clear for IntTfr Interrupt |
0x340 | DMA_CLEARBLOCK | Clear for IntBlock Interrupt |
0x348 | DMA_CLEARSRCTRAN | Clear for IntSrcTran Interrupt |
0x350 | DMA_CLEARDSTTRAN | Clear for IntDstTran IInterrupt |
0x358 | DMA_CLEARERR | Clear for IntErr Interrupt |
0x360 | DMA_STATUSINT | Status for each Interrupt Type |
0x368 | DMA_REQSRCREG | Source Software Transaction Request Register |
0x370 | DMA_REQDSTREG | Destination Software Transaction Request Register |
0x378 | DMA_SGLREQSRCREG | Single Source Software Transaction Request Register |
0x380 | DMA_SGLREQDSTREG | Single Destination Software Transaction Request Register |
0x388 | DMA_LSTREQSRCREG | Last Source Software Transaction Request Register |
0x390 | DMA_LSTREQDSTREG | Last Destination Software Transaction Request Register |
0x398 | DMA_DMACFGREG | DW_ahb_dmac Configuration Register |
0x3A0 | DMA_CHENREG | DW_ahb_dmac Channel Enable Register |
0x3A8 | DMA_DMAIDREG | DW_ahb_dmac ID Register |
0x3B0 | DMA_DMATESTREG | DW_ahb_dmac Test Register |
0x3B8 | DMA_VERSIONID | DW_ahb_dmac Version ID Register |
Function | Description |
---|---|
AT91F_DMA_Enable | Enable the DMA controller |
Offset | Name | Description |
---|---|---|
31..0 | DMA_SADD AT91C_DMA_SADD | Source Address of DMA Transfer |
Offset | Name | Description |
---|---|---|
31..0 | DMA_DADD AT91C_DMA_DADD | Destination Address of DMA Transfer |
Offset | Name | Description |
---|---|---|
31..0 | DMA_LOC AT91C_DMA_LOC | Address of the Next LLI |
Offset | Name | Description |
---|---|---|
0 | DMA_INT_EN AT91C_DMA_INT_EN | Interrupt Enable Bit |
3..1 | DMA_DST_TR_WIDTH AT91C_DMA_DST_TR_WIDTH | Destination Transfer Width |
6..4 | DMA_SRC_TR_WIDTH AT91C_DMA_SRC_TR_WIDTH | Source Transfer Width |
8..7 | DMA_DINC AT91C_DMA_DINC | Destination Address Increment |
10..9 | DMA_SINC AT91C_DMA_SINC | Source Address Increment |
13..11 | DMA_DEST_MSIZE AT91C_DMA_DEST_MSIZE | Destination Burst Transaction Length |
16..14 | DMA_SRC_MSIZE AT91C_DMA_SRC_MSIZE | Source Burst Transaction Length |
17 | DMA_S_GATH_EN AT91C_DMA_S_GATH_EN | Source Gather Enable Bit |
18 | DMA_D_SCAT_EN AT91C_DMA_D_SCAT_EN | Destination Scatter Enable Bit |
22..20 | DMA_TT_FC AT91C_DMA_TT_FC | Transfer Type and Flow Control |
24..23 | DMA_DMS AT91C_DMA_DMS | Destination Master Select |
26..25 | DMA_SMS AT91C_DMA_SMS | Source Master Select |
27 | DMA_LLP_D_EN AT91C_DMA_LLP_D_EN | Destination Block Chaining Enable |
28 | DMA_LLP_S_EN AT91C_DMA_LLP_S_EN | Source Block Chaining Enable |
Offset | Name | Description |
---|---|---|
11..0 | DMA_BLOCK_TS AT91C_DMA_BLOCK_TS | Block Transfer Size |
12 | DMA_DONE AT91C_DMA_DONE | Done bit |
Offset | Name | Description |
---|---|---|
7..5 | DMA_CH_PRIOR AT91C_DMA_CH_PRIOR | Channel Priority |
8 | DMA_CH_SUSP AT91C_DMA_CH_SUSP | Channel Suspend |
9 | DMA_FIFO_EMPT AT91C_DMA_FIFO_EMPT | Fifo Empty |
10 | DMA_HS_SEL_DS AT91C_DMA_HS_SEL_DS | Destination Software or Hardware Handshaking Select |
11 | DMA_HS_SEL_SR AT91C_DMA_HS_SEL_SR | Source Software or Hardware Handshaking Select |
13..12 | DMA_LOCK_CH_L AT91C_DMA_LOCK_CH_L | Channel Lock Level |
15..14 | DMA_LOCK_B_L AT91C_DMA_LOCK_B_L | Bus Lock Level |
16 | DMA_LOCK_CH AT91C_DMA_LOCK_CH | Channel Lock Bit |
17 | DMA_LOCK_B AT91C_DMA_LOCK_B | Bus Lock Bit |
18 | DMA_DS_HS_POL AT91C_DMA_DS_HS_POL | Destination Handshaking Interface Polarity |
19 | DMA_SR_HS_POL AT91C_DMA_SR_HS_POL | Source Handshaking Interface Polarity |
29..20 | DMA_MAX_ABRST AT91C_DMA_MAX_ABRST | Maximum AMBA Burst Length |
30 | DMA_RELOAD_SR AT91C_DMA_RELOAD_SR | Automatic Source Reload |
31 | DMA_RELOAD_DS AT91C_DMA_RELOAD_DS | Automatic Destination Reload |
Offset | Name | Description |
---|---|---|
0 | DMA_FCMODE AT91C_DMA_FCMODE | Flow Control Mode |
1 | DMA_FIFO_MODE AT91C_DMA_FIFO_MODE | Fifo Mode Select |
4..2 | DMA_PROTCTL AT91C_DMA_PROTCTL | Protection Control |
5 | DMA_DS_UPD_EN AT91C_DMA_DS_UPD_EN | Destination Status Update Enable |
6 | DMA_SS_UPD_EN AT91C_DMA_SS_UPD_EN | Source Status Update Enable |
10..7 | DMA_SRC_PER AT91C_DMA_SRC_PER | Source Hardware Handshaking Interface Assigns a h/w handshaking interface (0-DMAH_NUM_HS_INT-1) to the source of channel X if CFGx.HS_SEL_DST field is 0 |
14..11 | DMA_DEST_PER AT91C_DMA_DEST_PER | Destination Hardware Handshaking Interface |
Offset | Name | Description |
---|---|---|
19..0 | DMA_SGI AT91C_DMA_SGI | Source Gather Interval |
31..20 | DMA_SGC AT91C_DMA_SGC | Source Gather Count |
Offset | Name | Description |
---|---|---|
19..0 | DMA_DSI AT91C_DMA_DSI | Destination Scatter Interval |
31..20 | DMA_DSC AT91C_DMA_DSC | Destination Scatter Count |
Offset | Name | Description |
---|---|---|
31..0 | DMA_SADD AT91C_DMA_SADD | Source Address of DMA Transfer |
Offset | Name | Description |
---|---|---|
31..0 | DMA_DADD AT91C_DMA_DADD | Destination Address of DMA Transfer |
Offset | Name | Description |
---|---|---|
31..0 | DMA_LOC AT91C_DMA_LOC | Address of the Next LLI |
Offset | Name | Description |
---|---|---|
0 | DMA_INT_EN AT91C_DMA_INT_EN | Interrupt Enable Bit |
3..1 | DMA_DST_TR_WIDTH AT91C_DMA_DST_TR_WIDTH | Destination Transfer Width |
6..4 | DMA_SRC_TR_WIDTH AT91C_DMA_SRC_TR_WIDTH | Source Transfer Width |
8..7 | DMA_DINC AT91C_DMA_DINC | Destination Address Increment |
10..9 | DMA_SINC AT91C_DMA_SINC | Source Address Increment |
13..11 | DMA_DEST_MSIZE AT91C_DMA_DEST_MSIZE | Destination Burst Transaction Length |
16..14 | DMA_SRC_MSIZE AT91C_DMA_SRC_MSIZE | Source Burst Transaction Length |
17 | DMA_S_GATH_EN AT91C_DMA_S_GATH_EN | Source Gather Enable Bit |
18 | DMA_D_SCAT_EN AT91C_DMA_D_SCAT_EN | Destination Scatter Enable Bit |
22..20 | DMA_TT_FC AT91C_DMA_TT_FC | Transfer Type and Flow Control |
24..23 | DMA_DMS AT91C_DMA_DMS | Destination Master Select |
26..25 | DMA_SMS AT91C_DMA_SMS | Source Master Select |
27 | DMA_LLP_D_EN AT91C_DMA_LLP_D_EN | Destination Block Chaining Enable |
28 | DMA_LLP_S_EN AT91C_DMA_LLP_S_EN | Source Block Chaining Enable |
Offset | Name | Description |
---|---|---|
11..0 | DMA_BLOCK_TS AT91C_DMA_BLOCK_TS | Block Transfer Size |
12 | DMA_DONE AT91C_DMA_DONE | Done bit |
Offset | Name | Description |
---|---|---|
7..5 | DMA_CH_PRIOR AT91C_DMA_CH_PRIOR | Channel Priority |
8 | DMA_CH_SUSP AT91C_DMA_CH_SUSP | Channel Suspend |
9 | DMA_FIFO_EMPT AT91C_DMA_FIFO_EMPT | Fifo Empty |
10 | DMA_HS_SEL_DS AT91C_DMA_HS_SEL_DS | Destination Software or Hardware Handshaking Select |
11 | DMA_HS_SEL_SR AT91C_DMA_HS_SEL_SR | Source Software or Hardware Handshaking Select |
13..12 | DMA_LOCK_CH_L AT91C_DMA_LOCK_CH_L | Channel Lock Level |
15..14 | DMA_LOCK_B_L AT91C_DMA_LOCK_B_L | Bus Lock Level |
16 | DMA_LOCK_CH AT91C_DMA_LOCK_CH | Channel Lock Bit |
17 | DMA_LOCK_B AT91C_DMA_LOCK_B | Bus Lock Bit |
18 | DMA_DS_HS_POL AT91C_DMA_DS_HS_POL | Destination Handshaking Interface Polarity |
19 | DMA_SR_HS_POL AT91C_DMA_SR_HS_POL | Source Handshaking Interface Polarity |
29..20 | DMA_MAX_ABRST AT91C_DMA_MAX_ABRST | Maximum AMBA Burst Length |
30 | DMA_RELOAD_SR AT91C_DMA_RELOAD_SR | Automatic Source Reload |
31 | DMA_RELOAD_DS AT91C_DMA_RELOAD_DS | Automatic Destination Reload |
Offset | Name | Description |
---|---|---|
0 | DMA_FCMODE AT91C_DMA_FCMODE | Flow Control Mode |
1 | DMA_FIFO_MODE AT91C_DMA_FIFO_MODE | Fifo Mode Select |
4..2 | DMA_PROTCTL AT91C_DMA_PROTCTL | Protection Control |
5 | DMA_DS_UPD_EN AT91C_DMA_DS_UPD_EN | Destination Status Update Enable |
6 | DMA_SS_UPD_EN AT91C_DMA_SS_UPD_EN | Source Status Update Enable |
10..7 | DMA_SRC_PER AT91C_DMA_SRC_PER | Source Hardware Handshaking Interface Assigns a h/w handshaking interface (0-DMAH_NUM_HS_INT-1) to the source of channel X if CFGx.HS_SEL_DST field is 0 |
14..11 | DMA_DEST_PER AT91C_DMA_DEST_PER | Destination Hardware Handshaking Interface |
Offset | Name | Description |
---|---|---|
19..0 | DMA_SGI AT91C_DMA_SGI | Source Gather Interval |
31..20 | DMA_SGC AT91C_DMA_SGC | Source Gather Count |
Offset | Name | Description |
---|---|---|
19..0 | DMA_DSI AT91C_DMA_DSI | Destination Scatter Interval |
31..20 | DMA_DSC AT91C_DMA_DSC | Destination Scatter Count |
Offset | Name | Description |
---|---|---|
2..0 | DMA_RAW AT91C_DMA_RAW | Raw Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_RAW AT91C_DMA_RAW | Raw Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_RAW AT91C_DMA_RAW | Raw Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_RAW AT91C_DMA_RAW | Raw Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_RAW AT91C_DMA_RAW | Raw Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_STATUS AT91C_DMA_STATUS | Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_STATUS AT91C_DMA_STATUS | Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_STATUS AT91C_DMA_STATUS | Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_STATUS AT91C_DMA_STATUS | Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_RAW AT91C_DMA_RAW | Raw Interrupt for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_INT_MASK AT91C_DMA_INT_MASK | Interrupt Mask for each Channel |
10..8 | DMA_INT_M_WE AT91C_DMA_INT_M_WE | Interrupt Mask Write Enable for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_INT_MASK AT91C_DMA_INT_MASK | Interrupt Mask for each Channel |
10..8 | DMA_INT_M_WE AT91C_DMA_INT_M_WE | Interrupt Mask Write Enable for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_INT_MASK AT91C_DMA_INT_MASK | Interrupt Mask for each Channel |
10..8 | DMA_INT_M_WE AT91C_DMA_INT_M_WE | Interrupt Mask Write Enable for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_INT_MASK AT91C_DMA_INT_MASK | Interrupt Mask for each Channel |
10..8 | DMA_INT_M_WE AT91C_DMA_INT_M_WE | Interrupt Mask Write Enable for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_INT_MASK AT91C_DMA_INT_MASK | Interrupt Mask for each Channel |
10..8 | DMA_INT_M_WE AT91C_DMA_INT_M_WE | Interrupt Mask Write Enable for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_CLEAR AT91C_DMA_CLEAR | Interrupt Clear for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_CLEAR AT91C_DMA_CLEAR | Interrupt Clear for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_CLEAR AT91C_DMA_CLEAR | Interrupt Clear for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_CLEAR AT91C_DMA_CLEAR | Interrupt Clear for each Channel |
Offset | Name | Description |
---|---|---|
2..0 | DMA_CLEAR AT91C_DMA_CLEAR | Interrupt Clear for each Channel |
Offset | Name | Description |
---|---|---|
0 | DMA_TFR AT91C_DMA_TFR | OR of the content of StatusTfr Register |
1 | DMA_BLOCK AT91C_DMA_BLOCK | OR of the content of StatusBlock Register |
2 | DMA_SRCT AT91C_DMA_SRCT | OR of the content of StatusSrcTran Register |
3 | DMA_DSTT AT91C_DMA_DSTT | OR of the content of StatusDstTran Register |
4 | DMA_ERR AT91C_DMA_ERR | OR of the content of StatusErr Register |
Offset | Name | Description |
---|---|---|
2..0 | DMA_SRC_REQ AT91C_DMA_SRC_REQ | Source Request |
10..8 | DMA_REQ_WE AT91C_DMA_REQ_WE | Request Write Enable |
Offset | Name | Description |
---|---|---|
2..0 | DMA_DST_REQ AT91C_DMA_DST_REQ | Destination Request |
10..8 | DMA_REQ_WE AT91C_DMA_REQ_WE | Request Write Enable |
Offset | Name | Description |
---|---|---|
2..0 | DMA_S_SG_REQ AT91C_DMA_S_SG_REQ | Source Single Request |
10..8 | DMA_REQ_WE AT91C_DMA_REQ_WE | Request Write Enable |
Offset | Name | Description |
---|---|---|
2..0 | DMA_D_SG_REQ AT91C_DMA_D_SG_REQ | Destination Single Request |
10..8 | DMA_REQ_WE AT91C_DMA_REQ_WE | Request Write Enable |
Offset | Name | Description |
---|---|---|
2..0 | DMA_LSTSRC AT91C_DMA_LSTSRC | Source Last Transaction Request |
10..8 | DMA_LSTSR_WE AT91C_DMA_LSTSR_WE | Source Last Transaction Request Write Enable |
Offset | Name | Description |
---|---|---|
2..0 | DMA_LSTDST AT91C_DMA_LSTDST | Destination Last Transaction Request |
10..8 | DMA_LSTDS_WE AT91C_DMA_LSTDS_WE | Destination Last Transaction Request Write Enable |
Offset | Name | Description |
---|---|---|
2..0 | DMA_DMA_EN AT91C_DMA_DMA_EN | Controller Enable |
Offset | Name | Description |
---|---|---|
2..0 | DMA_CH_EN AT91C_DMA_CH_EN | Channel Enable |
10..8 | DMA_CH_EN_WE AT91C_DMA_CH_EN_WE | Channel Enable Write Enable |
Offset | Name | Description |
---|---|---|
0 | DMA_TEST_SLV_IF AT91C_DMA_TEST_SLV_IF | Test Mode for Slave Interface |