Power Management Controler Peripheral

PMC (AT91S_PMC) 0xFFFFFC00 (AT91C_BASE_PMC)
Periph ID AICSymbolDescription
1 (AT91C_ID_SYS)System Interrupt

SignalSymbolPIO controllerDescription
PCK1(AT91C_PC31_PCK1 )PIOC Periph: B Bit: 31PMC Programmable clock Output 1
PCK1(AT91C_PA8_PCK1 )PIOA Periph: B Bit: 8PMC Programmable clock Output 1
PCK2(AT91C_PC8_PCK2 )PIOC Periph: B Bit: 8PMC Programmable clock Output 2
PCK2(AT91C_PB31_PCK2 )PIOB Periph: B Bit: 31PMC Programmable clock Output 2
PCK2(AT91C_PA9_PCK2 )PIOA Periph: B Bit: 9PMC Programmable clock Output 2
PCK3(AT91C_PC9_PCK3 )PIOC Periph: B Bit: 9PMC Programmable clock Output 3
PCK3(AT91C_PA10_PCK3 )PIOA Periph: B Bit: 10PMC Programmable clock Output 3
PCK0(AT91C_PA7_PCK0 )PIOA Periph: B Bit: 7PMC Programmable clock Output 0
PCK0(AT91C_PB2_PCK0 )PIOB Periph: B Bit: 2PMC Programmable clock Output 0

FunctionDescription
AT91F_PMC_CfgPMCEnable Peripheral clock in PMC for PMC
AT91F_PMC_CfgPIOConfigure PIO controllers to drive PMC signals


PMC Software API (AT91S_PMC)

OffsetFieldDescription
0x0PMC_SCERSystem Clock Enable Register
0x4PMC_SCDRSystem Clock Disable Register
0x8PMC_SCSRSystem Clock Status Register
0x10PMC_PCERPeripheral Clock Enable Register
0x14PMC_PCDRPeripheral Clock Disable Register
0x18PMC_PCSRPeripheral Clock Status Register
0x20PMC_MOR (CKGR_MOR)Main Oscillator Register
0x24PMC_MCFR (CKGR_MCFR)Main Clock Frequency Register
0x28PMC_PLLAR (CKGR_PLLAR)PLL A Register
0x2CPMC_PLLBR (CKGR_PLLBR)PLL B Register
0x30PMC_MCKRMaster Clock Register
0x40PMC_PCKR[8] (PMC_PCKR)Programmable Clock Register
0x60PMC_IERInterrupt Enable Register
0x64PMC_IDRInterrupt Disable Register
0x68PMC_SRStatus Register
0x6CPMC_IMRInterrupt Mask Register

FunctionDescription
AT91F_CKGR_CfgPLLB_TransientTimeCfg PLL oscount field according to the PLL transient time
AT91F_PMC_GetInterruptMaskStatusReturn PMC Interrupt Mask Status
AT91F_CKGR_DisableMainOscillatorDisable the main oscillator
AT91F_CKGR_GetMainOscillatorRegCfg the main oscillator
AT91F_CKGR_GetMainClockReturn Main clock in Hz
AT91F_PMC_CfgSysClkDisableRegConfigure the System Clock Disable Register of the PMC controller
AT91F_CKGR_DisablePLLBInputDisable the PLLB Input
AT91F_PMC_IsInterruptMaskedTest if PMC Interrupt is Masked
AT91F_PMC_EnableItEnable PMC interrupt
AT91F_PMC_GetPeriphClockGet peripheral clock status
AT91F_CKGR_CfgPLLA_TransientTimeCfg PLL oscount field according to the PLL transient time
AT91F_PMC_EnablePCKEnable peripheral clock
AT91F_PMC_GetMCKRegReturn Master Clock Register
AT91F_CKGR_EnableMainOscillatorEnable the main oscillator
AT91F_CKGR_GetMainClockFreqRegCfg the main oscillator
AT91F_PMC_DisableHCKDisable AHB peripheral clock
AT91F_CKGR_CfgPLLARegCfg the PLLA Register
AT91F_PMC_GetMasterClockReturn master clock in Hz
AT91F_CKGR_CfgPLLBRegCfg the PLLB Register
AT91F_PMC_GetStatusReturn PMC Interrupt Status
AT91F_CKGR_CfgMainOscillatorRegCfg the main oscillator
AT91F_CKGR_GetPLLARegGet the PLLA Register
AT91F_CKGR_GetPLLBRegGet the PLLB Register
AT91F_PMC_GetProcessorClockReturn processor clock in Hz
AT91F_CKGR_DisablePLLBOutputDisable the PLLB output
AT91F_CKGR_DisablePLLAInputDisable the PLLA Input
AT91F_PMC_CfgSysClkEnableRegConfigure the System Clock Enable Register of the PMC controller
AT91F_PMC_EnablePeriphClockEnable peripheral clock
AT91F_PMC_DisablePeriphClockDisable peripheral clock
AT91F_PMC_DisablePCKEnable peripheral clock
AT91F_PMC_GetSysClkStatusRegReturn the System Clock Status Register of the PMC controller
AT91F_PMC_IsStatusSetTest if PMC Status is Set
AT91F_PMC_DisableItDisable PMC interrupt
AT91F_CKGR_CfgMainOscStartUpTimeCfg MOR Register according to the main osc startup time
AT91F_PMC_EnableHCKEnable AHB peripheral clock
AT91F_CKGR_DisablePLLAOutputDisable the PLLA output
AT91F_CKGR_DisablePLLADisable the PLLA input and output for conso reduction
AT91F_PMC_CfgMCKRegCfg Master Clock Register
AT91F_CKGR_DisablePLLBDisable the PLLB input and output for conso reduction

PMC Register Description

PMC: AT91_REG PMC_SCER System Clock Enable Register

OffsetNameDescription
0PMC_PCK
AT91C_PMC_PCK
Processor Clock
0 = The processor clock is disabled
1 = The processor clock is enabled
6PMC_UHP
AT91C_PMC_UHP
USB Host Port Clock
0 = The 12/48 MHz clock of the USB Host Port is disabled.
1 = The 12/48 MHz clock of the USB Host Port is enabled.
7PMC_UDP
AT91C_PMC_UDP
USB Device Port Clock
0 = The 48 MHz clock of the USB Device Port is disabled
1 = The 48 MHz clock of the USB Device Port is enabled
8PMC_PCK0
AT91C_PMC_PCK0
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
9PMC_PCK1
AT91C_PMC_PCK1
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
10PMC_PCK2
AT91C_PMC_PCK2
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
11PMC_PCK3
AT91C_PMC_PCK3
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
16PMC_HCK0
AT91C_PMC_HCK0
AHB UHP Clock Output
0 = The corresponding AHB UHP clock output is disabled.
1 = The corresponding AHB UHP clock output is enabled.
17PMC_HCK1
AT91C_PMC_HCK1
AHB LCDC Clock Output
0 = The corresponding AHB LCDC clock output is disabled.
1 = The corresponding AHB LCDC clock output is enabled.

PMC: AT91_REG PMC_SCDR System Clock Disable Register

OffsetNameDescription
0PMC_PCK
AT91C_PMC_PCK
Processor Clock
0 = The processor clock is disabled
1 = The processor clock is enabled
6PMC_UHP
AT91C_PMC_UHP
USB Host Port Clock
0 = The 12/48 MHz clock of the USB Host Port is disabled.
1 = The 12/48 MHz clock of the USB Host Port is enabled.
7PMC_UDP
AT91C_PMC_UDP
USB Device Port Clock
0 = The 48 MHz clock of the USB Device Port is disabled
1 = The 48 MHz clock of the USB Device Port is enabled
8PMC_PCK0
AT91C_PMC_PCK0
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
9PMC_PCK1
AT91C_PMC_PCK1
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
10PMC_PCK2
AT91C_PMC_PCK2
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
11PMC_PCK3
AT91C_PMC_PCK3
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
16PMC_HCK0
AT91C_PMC_HCK0
AHB UHP Clock Output
0 = The corresponding AHB UHP clock output is disabled.
1 = The corresponding AHB UHP clock output is enabled.
17PMC_HCK1
AT91C_PMC_HCK1
AHB LCDC Clock Output
0 = The corresponding AHB LCDC clock output is disabled.
1 = The corresponding AHB LCDC clock output is enabled.

PMC: AT91_REG PMC_SCSR System Clock Status Register

OffsetNameDescription
0PMC_PCK
AT91C_PMC_PCK
Processor Clock
0 = The processor clock is disabled
1 = The processor clock is enabled
6PMC_UHP
AT91C_PMC_UHP
USB Host Port Clock
0 = The 12/48 MHz clock of the USB Host Port is disabled.
1 = The 12/48 MHz clock of the USB Host Port is enabled.
7PMC_UDP
AT91C_PMC_UDP
USB Device Port Clock
0 = The 48 MHz clock of the USB Device Port is disabled
1 = The 48 MHz clock of the USB Device Port is enabled
8PMC_PCK0
AT91C_PMC_PCK0
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
9PMC_PCK1
AT91C_PMC_PCK1
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
10PMC_PCK2
AT91C_PMC_PCK2
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
11PMC_PCK3
AT91C_PMC_PCK3
Programmable Clock Output
0 = The corresponding programmable clock output is disabled.
1 = The corresponding programmable clock output is enabled.
16PMC_HCK0
AT91C_PMC_HCK0
AHB UHP Clock Output
0 = The corresponding AHB UHP clock output is disabled.
1 = The corresponding AHB UHP clock output is enabled.
17PMC_HCK1
AT91C_PMC_HCK1
AHB LCDC Clock Output
0 = The corresponding AHB LCDC clock output is disabled.
1 = The corresponding AHB LCDC clock output is enabled.

PMC: AT91_REG PMC_PCER Peripheral Clock Enable Register


PID2...PID31: Peripheral Identifier 2 to 31
0 = No effect.
1 = Enables the peripheral clock.

PMC: AT91_REG PMC_PCDR Peripheral Clock Disable Register


PID2...PID31: Peripheral Identifier 2 to 31
0 = No effect.
1 = Disables the peripheral clock.

PMC: AT91_REG PMC_PCSR Peripheral Clock Status Register


PID2...PID31: Peripheral Identifier 2 to 31
0 = peripheral clock disabled.
1 = peripheral clock enabled.

PMC: AT91_REG CKGR_MOR Main Oscillator Register

OffsetNameDescription
0CKGR_MOSCEN
AT91C_CKGR_MOSCEN
Main Oscillator Enable
0 = The main oscillator is disabled.
1 = The main oscillator is enabled. OSCBYPASS must be set to 0.
1CKGR_OSCBYPASS
AT91C_CKGR_OSCBYPASS
Main Oscillator Bypass
0 = The main oscillator is not bypassed.
1 = The main oscillator is bypassed. MOSCEN bit must be set to 0.
15..8CKGR_OSCOUNT
AT91C_CKGR_OSCOUNT
Main Oscillator Start-up Time
Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.

PMC: AT91_REG CKGR_MCFR Main Clock Frequency Register

OffsetNameDescription
15..0CKGR_MAINF
AT91C_CKGR_MAINF
Main Clock Frequency
Gives the number of main clock cycles within 16 slow clock periods.
16CKGR_MAINRDY
AT91C_CKGR_MAINRDY
Main Clock Ready
0 = FMAIN value is not valid or the main oscillator is disabled.
1 = The main oscillator has been enabled previously and MAINF value is available.

PMC: AT91_REG CKGR_PLLAR PLL A Register

OffsetNameDescription
7..0CKGR_DIVA
AT91C_CKGR_DIVA
Divider A Selected
2-255 Divider output is the selected clock divided by DIVA
ValueLabelDescription
0CKGR_DIVA_0
AT91C_CKGR_DIVA_0

Divider A output is 0
1CKGR_DIVA_BYPASS
AT91C_CKGR_DIVA_BYPASS

Divider A is bypassed
13..8CKGR_PLLACOUNT
AT91C_CKGR_PLLACOUNT
PLL A Counter
Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after PMC_PLLA is written.
15..14CKGR_OUTA
AT91C_CKGR_OUTA
PLL A Output Frequency Range
ValueLabelDescription
0CKGR_OUTA_0
AT91C_CKGR_OUTA_0

Please refer to the PLLA datasheet
1CKGR_OUTA_1
AT91C_CKGR_OUTA_1

Please refer to the PLLA datasheet
2CKGR_OUTA_2
AT91C_CKGR_OUTA_2

Please refer to the PLLA datasheet
3CKGR_OUTA_3
AT91C_CKGR_OUTA_3

Please refer to the PLLA datasheet
26..16CKGR_MULA
AT91C_CKGR_MULA
PLL A Multiplier
0 = The PLL A is deactivated.
1 up to 2047 = The PLL A output frequency is the PLL A input frequency multiplied by MULA + 1.
29CKGR_SRCA
AT91C_CKGR_SRCA

BE CAREFUL !!! This bit MUST BE SET TO 1.

PMC: AT91_REG CKGR_PLLBR PLL B Register

OffsetNameDescription
7..0CKGR_DIVB
AT91C_CKGR_DIVB
Divider B Selected
2-255 Divider output is the selected clock divided by DIVB
ValueLabelDescription
0CKGR_DIVB_0
AT91C_CKGR_DIVB_0

Divider B output is 0
1CKGR_DIVB_BYPASS
AT91C_CKGR_DIVB_BYPASS

Divider B is bypassed
13..8CKGR_PLLBCOUNT
AT91C_CKGR_PLLBCOUNT
PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after PMC_PLLB is written.
15..14CKGR_OUTB
AT91C_CKGR_OUTB
PLL B Output Frequency Range
ValueLabelDescription
0CKGR_OUTB_0
AT91C_CKGR_OUTB_0

Please refer to the PLLB datasheet
1CKGR_OUTB_1
AT91C_CKGR_OUTB_1

Please refer to the PLLB datasheet
2CKGR_OUTB_2
AT91C_CKGR_OUTB_2

Please refer to the PLLB datasheet
3CKGR_OUTB_3
AT91C_CKGR_OUTB_3

Please refer to the PLLB datasheet
26..16CKGR_MULB
AT91C_CKGR_MULB
PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 2047 = The PLL B output frequency is the PLL B input frequency multiplied by MULB + 1.
29..28CKGR_USBDIV
AT91C_CKGR_USBDIV
Divider for USB Clocks
ValueLabelDescription
0CKGR_USBDIV_0
AT91C_CKGR_USBDIV_0

Divider output is PLL clock output
1CKGR_USBDIV_1
AT91C_CKGR_USBDIV_1

Divider output is PLL clock output divided by 2
2CKGR_USBDIV_2
AT91C_CKGR_USBDIV_2

Divider output is PLL clock output divided by 4

PMC: AT91_REG PMC_MCKR Master Clock Register

OffsetNameDescription
1..0PMC_CSS
AT91C_PMC_CSS
Programmable Clock Selection
Clock selection
ValueLabelDescription
0PMC_CSS_SLOW_CLK
AT91C_PMC_CSS_SLOW_CLK

Slow Clock is selected
1PMC_CSS_MAIN_CLK
AT91C_PMC_CSS_MAIN_CLK

Main Clock is selected
2PMC_CSS_PLLA_CLK
AT91C_PMC_CSS_PLLA_CLK

Clock from PLL A is selected
3PMC_CSS_PLLB_CLK
AT91C_PMC_CSS_PLLB_CLK

Clock from PLL B is selected
4..2PMC_PRES
AT91C_PMC_PRES
Programmable Clock Prescaler
Master clock
ValueLabelDescription
0PMC_PRES_CLK
AT91C_PMC_PRES_CLK

Selected clock
1PMC_PRES_CLK_2
AT91C_PMC_PRES_CLK_2

Selected clock divided by 2
2PMC_PRES_CLK_4
AT91C_PMC_PRES_CLK_4

Selected clock divided by 4
3PMC_PRES_CLK_8
AT91C_PMC_PRES_CLK_8

Selected clock divided by 8
4PMC_PRES_CLK_16
AT91C_PMC_PRES_CLK_16

Selected clock divided by 16
5PMC_PRES_CLK_32
AT91C_PMC_PRES_CLK_32

Selected clock divided by 32
6PMC_PRES_CLK_64
AT91C_PMC_PRES_CLK_64

Selected clock divided by 64
9..8PMC_MDIV
AT91C_PMC_MDIV
Master Clock Division
ValueLabelDescription
0PMC_MDIV_1
AT91C_PMC_MDIV_1

The master clock and the processor clock are the same
1PMC_MDIV_2
AT91C_PMC_MDIV_2

The processor clock is twice as fast as the master clock
2PMC_MDIV_3
AT91C_PMC_MDIV_3

The processor clock is four times faster than the master clock

PMC: AT91_REG PMC_PCKR Programmable Clock Register

OffsetNameDescription
1..0PMC_CSS
AT91C_PMC_CSS
Programmable Clock Selection
Clock selection
ValueLabelDescription
0PMC_CSS_SLOW_CLK
AT91C_PMC_CSS_SLOW_CLK

Slow Clock is selected
1PMC_CSS_MAIN_CLK
AT91C_PMC_CSS_MAIN_CLK

Main Clock is selected
2PMC_CSS_PLLA_CLK
AT91C_PMC_CSS_PLLA_CLK

Clock from PLL A is selected
3PMC_CSS_PLLB_CLK
AT91C_PMC_CSS_PLLB_CLK

Clock from PLL B is selected
4..2PMC_PRES
AT91C_PMC_PRES
Programmable Clock Prescaler
Master clock
ValueLabelDescription
0PMC_PRES_CLK
AT91C_PMC_PRES_CLK

Selected clock
1PMC_PRES_CLK_2
AT91C_PMC_PRES_CLK_2

Selected clock divided by 2
2PMC_PRES_CLK_4
AT91C_PMC_PRES_CLK_4

Selected clock divided by 4
3PMC_PRES_CLK_8
AT91C_PMC_PRES_CLK_8

Selected clock divided by 8
4PMC_PRES_CLK_16
AT91C_PMC_PRES_CLK_16

Selected clock divided by 16
5PMC_PRES_CLK_32
AT91C_PMC_PRES_CLK_32

Selected clock divided by 32
6PMC_PRES_CLK_64
AT91C_PMC_PRES_CLK_64

Selected clock divided by 64

PMC: AT91_REG PMC_IER Interrupt Enable Register

OffsetNameDescription
0PMC_MOSCS
AT91C_PMC_MOSCS
MOSC Status/Enable/Disable/Mask
0 = Main oscillator is not stabilized.
1 = Main oscillator is stabilized.
1PMC_LOCKA
AT91C_PMC_LOCKA
PLL A Status/Enable/Disable/Mask
0 = PLLA is not locked.
1 = PLLA is locked.
2PMC_LOCKB
AT91C_PMC_LOCKB
PLL B Status/Enable/Disable/Mask
0 = PLLB is not locked.
1 = PLLB is locked.
3PMC_MCKRDY
AT91C_PMC_MCKRDY
Master Clock Status/Enable/Disable/Mask
0 = MCK Clock is not ready to be turned on.
1 = MCK Clock is ready to be turned on.
8PMC_PCK0RDY
AT91C_PMC_PCK0RDY
PCK0_RDY Status/Enable/Disable/Mask
0 = Pad Clock0 is not ready to be turned on.
1 = Pad Clock0 is ready to be turned on.
9PMC_PCK1RDY
AT91C_PMC_PCK1RDY
PCK1_RDY Status/Enable/Disable/Mask
0 = Pad Clock1 is not ready to be turned on.
1 = Pad Clock1 is ready to be turned on.
10PMC_PCK2RDY
AT91C_PMC_PCK2RDY
PCK2_RDY Status/Enable/Disable/Mask
0 = Pad Clock2 is not ready to be turned on.
1 = Pad Clock2 is ready to be turned on.
11PMC_PCK3RDY
AT91C_PMC_PCK3RDY
PCK3_RDY Status/Enable/Disable/Mask
0 = Pad Clock3 is not ready to be turned on.
1 = Pad Clock3 is ready to be turned on.

PMC: AT91_REG PMC_IDR Interrupt Disable Register

OffsetNameDescription
0PMC_MOSCS
AT91C_PMC_MOSCS
MOSC Status/Enable/Disable/Mask
0 = Main oscillator is not stabilized.
1 = Main oscillator is stabilized.
1PMC_LOCKA
AT91C_PMC_LOCKA
PLL A Status/Enable/Disable/Mask
0 = PLLA is not locked.
1 = PLLA is locked.
2PMC_LOCKB
AT91C_PMC_LOCKB
PLL B Status/Enable/Disable/Mask
0 = PLLB is not locked.
1 = PLLB is locked.
3PMC_MCKRDY
AT91C_PMC_MCKRDY
Master Clock Status/Enable/Disable/Mask
0 = MCK Clock is not ready to be turned on.
1 = MCK Clock is ready to be turned on.
8PMC_PCK0RDY
AT91C_PMC_PCK0RDY
PCK0_RDY Status/Enable/Disable/Mask
0 = Pad Clock0 is not ready to be turned on.
1 = Pad Clock0 is ready to be turned on.
9PMC_PCK1RDY
AT91C_PMC_PCK1RDY
PCK1_RDY Status/Enable/Disable/Mask
0 = Pad Clock1 is not ready to be turned on.
1 = Pad Clock1 is ready to be turned on.
10PMC_PCK2RDY
AT91C_PMC_PCK2RDY
PCK2_RDY Status/Enable/Disable/Mask
0 = Pad Clock2 is not ready to be turned on.
1 = Pad Clock2 is ready to be turned on.
11PMC_PCK3RDY
AT91C_PMC_PCK3RDY
PCK3_RDY Status/Enable/Disable/Mask
0 = Pad Clock3 is not ready to be turned on.
1 = Pad Clock3 is ready to be turned on.

PMC: AT91_REG PMC_SR Status Register

OffsetNameDescription
0PMC_MOSCS
AT91C_PMC_MOSCS
MOSC Status/Enable/Disable/Mask
0 = Main oscillator is not stabilized.
1 = Main oscillator is stabilized.
1PMC_LOCKA
AT91C_PMC_LOCKA
PLL A Status/Enable/Disable/Mask
0 = PLLA is not locked.
1 = PLLA is locked.
2PMC_LOCKB
AT91C_PMC_LOCKB
PLL B Status/Enable/Disable/Mask
0 = PLLB is not locked.
1 = PLLB is locked.
3PMC_MCKRDY
AT91C_PMC_MCKRDY
Master Clock Status/Enable/Disable/Mask
0 = MCK Clock is not ready to be turned on.
1 = MCK Clock is ready to be turned on.
8PMC_PCK0RDY
AT91C_PMC_PCK0RDY
PCK0_RDY Status/Enable/Disable/Mask
0 = Pad Clock0 is not ready to be turned on.
1 = Pad Clock0 is ready to be turned on.
9PMC_PCK1RDY
AT91C_PMC_PCK1RDY
PCK1_RDY Status/Enable/Disable/Mask
0 = Pad Clock1 is not ready to be turned on.
1 = Pad Clock1 is ready to be turned on.
10PMC_PCK2RDY
AT91C_PMC_PCK2RDY
PCK2_RDY Status/Enable/Disable/Mask
0 = Pad Clock2 is not ready to be turned on.
1 = Pad Clock2 is ready to be turned on.
11PMC_PCK3RDY
AT91C_PMC_PCK3RDY
PCK3_RDY Status/Enable/Disable/Mask
0 = Pad Clock3 is not ready to be turned on.
1 = Pad Clock3 is ready to be turned on.

PMC: AT91_REG PMC_IMR Interrupt Mask Register

OffsetNameDescription
0PMC_MOSCS
AT91C_PMC_MOSCS
MOSC Status/Enable/Disable/Mask
0 = Main oscillator is not stabilized.
1 = Main oscillator is stabilized.
1PMC_LOCKA
AT91C_PMC_LOCKA
PLL A Status/Enable/Disable/Mask
0 = PLLA is not locked.
1 = PLLA is locked.
2PMC_LOCKB
AT91C_PMC_LOCKB
PLL B Status/Enable/Disable/Mask
0 = PLLB is not locked.
1 = PLLB is locked.
3PMC_MCKRDY
AT91C_PMC_MCKRDY
Master Clock Status/Enable/Disable/Mask
0 = MCK Clock is not ready to be turned on.
1 = MCK Clock is ready to be turned on.
8PMC_PCK0RDY
AT91C_PMC_PCK0RDY
PCK0_RDY Status/Enable/Disable/Mask
0 = Pad Clock0 is not ready to be turned on.
1 = Pad Clock0 is ready to be turned on.
9PMC_PCK1RDY
AT91C_PMC_PCK1RDY
PCK1_RDY Status/Enable/Disable/Mask
0 = Pad Clock1 is not ready to be turned on.
1 = Pad Clock1 is ready to be turned on.
10PMC_PCK2RDY
AT91C_PMC_PCK2RDY
PCK2_RDY Status/Enable/Disable/Mask
0 = Pad Clock2 is not ready to be turned on.
1 = Pad Clock2 is ready to be turned on.
11PMC_PCK3RDY
AT91C_PMC_PCK3RDY
PCK3_RDY Status/Enable/Disable/Mask
0 = Pad Clock3 is not ready to be turned on.
1 = Pad Clock3 is ready to be turned on.