Signal | Symbol | PIO controller | Description |
---|---|---|---|
NCS5_CFCS1 | (AT91C_PC5_NCS5_CFCS1) | PIOC Periph: A Bit: 5 | Chip Select 5 / CompactFlash Chip Select 1 |
NCS4_CFCS0 | (AT91C_PC4_NCS4_CFCS0) | PIOC Periph: A Bit: 4 | Chip Select 4 / CompactFlash Chip Select 0 |
A25_CFRNW | (AT91C_PC3_A25_CFRNW) | PIOC Periph: A Bit: 3 | Address Bus[25] / Compact Flash Read Not Write |
CFCE1 | (AT91C_PC6_CFCE1 ) | PIOC Periph: A Bit: 6 | CompactFlash Chip Enable 1 |
CFCE2 | (AT91C_PC7_CFCE2 ) | PIOC Periph: A Bit: 7 | CompactFlash Chip Enable 2 |
SMWE | (AT91C_PC1_SMWE ) | PIOC Periph: A Bit: 1 | SmartMedia Write Enable |
SMOE | (AT91C_PC0_SMOE ) | PIOC Periph: A Bit: 0 | SmartMedia Output Enable |
Function | Description |
---|---|
AT91F_SMC_CfgPIO | Configure PIO controllers to drive SMC signals |
Offset | Field | Description |
---|---|---|
0x0 | SMC_SETUP0 (SMC_SETUP) | Setup Register for CS 0 |
0x4 | SMC_PULSE0 (SMC_PULSE) | Pulse Register for CS 0 |
0x8 | SMC_CYCLE0 (SMC_CYC) | Cycle Register for CS 0 |
0xC | SMC_CTRL0 (SMC_CTRL) | Control Register for CS 0 |
0x10 | SMC_SETUP1 (SMC_SETUP) | Setup Register for CS 1 |
0x14 | SMC_PULSE1 (SMC_PULSE) | Pulse Register for CS 1 |
0x18 | SMC_CYCLE1 (SMC_CYC) | Cycle Register for CS 1 |
0x1C | SMC_CTRL1 (SMC_CTRL) | Control Register for CS 1 |
0x20 | SMC_SETUP2 (SMC_SETUP) | Setup Register for CS 2 |
0x24 | SMC_PULSE2 (SMC_PULSE) | Pulse Register for CS 2 |
0x28 | SMC_CYCLE2 (SMC_CYC) | Cycle Register for CS 2 |
0x2C | SMC_CTRL2 (SMC_CTRL) | Control Register for CS 2 |
0x30 | SMC_SETUP3 (SMC_SETUP) | Setup Register for CS 3 |
0x34 | SMC_PULSE3 (SMC_PULSE) | Pulse Register for CS 3 |
0x38 | SMC_CYCLE3 (SMC_CYC) | Cycle Register for CS 3 |
0x3C | SMC_CTRL3 (SMC_CTRL) | Control Register for CS 3 |
0x40 | SMC_SETUP4 (SMC_SETUP) | Setup Register for CS 4 |
0x44 | SMC_PULSE4 (SMC_PULSE) | Pulse Register for CS 4 |
0x48 | SMC_CYCLE4 (SMC_CYC) | Cycle Register for CS 4 |
0x4C | SMC_CTRL4 (SMC_CTRL) | Control Register for CS 4 |
0x50 | SMC_SETUP5 (SMC_SETUP) | Setup Register for CS 5 |
0x54 | SMC_PULSE5 (SMC_PULSE) | Pulse Register for CS 5 |
0x58 | SMC_CYCLE5 (SMC_CYC) | Cycle Register for CS 5 |
0x5C | SMC_CTRL5 (SMC_CTRL) | Control Register for CS 5 |
0x60 | SMC_SETUP6 (SMC_SETUP) | Setup Register for CS 6 |
0x64 | SMC_PULSE6 (SMC_PULSE) | Pulse Register for CS 6 |
0x68 | SMC_CYCLE6 (SMC_CYC) | Cycle Register for CS 6 |
0x6C | SMC_CTRL6 (SMC_CTRL) | Control Register for CS 6 |
0x70 | SMC_SETUP7 (SMC_SETUP) | Setup Register for CS 7 |
0x74 | SMC_PULSE7 (SMC_PULSE) | Pulse Register for CS 7 |
0x78 | SMC_CYCLE7 (SMC_CYC) | Cycle Register for CS 7 |
0x7C | SMC_CTRL7 (SMC_CTRL) | Control Register for CS 7 |
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|
Offset | Name | Description |
---|---|---|
5..0 | SMC_NWESETUP AT91C_SMC_NWESETUP | NWE Setup Length NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0] |
13..8 | SMC_NCSSETUPWR AT91C_SMC_NCSSETUPWR | NCS Setup Length in WRite Access NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0] |
21..16 | SMC_NRDSETUP AT91C_SMC_NRDSETUP | NRD Setup Length NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0] |
29..24 | SMC_NCSSETUPRD AT91C_SMC_NCSSETUPRD | NCS Setup Length in ReaD Access NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0] |
Offset | Name | Description |
---|---|---|
6..0 | SMC_NWEPULSE AT91C_SMC_NWEPULSE | NWE Pulse Length NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0] |
14..8 | SMC_NCSPULSEWR AT91C_SMC_NCSPULSEWR | NCS Pulse Length in WRite Access NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0] |
22..16 | SMC_NRDPULSE AT91C_SMC_NRDPULSE | NRD Pulse Length NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0] |
30..24 | SMC_NCSPULSERD AT91C_SMC_NCSPULSERD | NCS Pulse Length in ReaD Access NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0] |
Offset | Name | Description |
---|---|---|
8..0 | SMC_NWECYCLE AT91C_SMC_NWECYCLE | Total Write Cycle Length Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0] |
24..16 | SMC_NRDCYCLE AT91C_SMC_NRDCYCLE | Total Read Cycle Length Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0] |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | SMC_READMODE AT91C_SMC_READMODE | Read Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NRD signal. | |||||||||||||||
1 | SMC_WRITEMODE AT91C_SMC_WRITEMODE | Write Mode 0: Read operation controled by NCS signal. 1: Read operation controled by NWE signal. | |||||||||||||||
6..5 | SMC_NWAITM AT91C_SMC_NWAITM | NWAIT Mode 0: External NWAIT disabled 1: Reserved. 2: External NWAIT enabled in frozen mode. 3: External NWAIT enabled in ready mode.
| |||||||||||||||
8 | SMC_BAT AT91C_SMC_BAT | Byte Access Type 0: Byte Select. 1: Byte Write.
| |||||||||||||||
13..12 | SMC_DBW AT91C_SMC_DBW | Data Bus Width 0: 8 bits. 1: 16 bits. 3: 32 bits. 4: Reserved
| |||||||||||||||
19..16 | SMC_TDF AT91C_SMC_TDF | Data Float Time. 0 up to 15 cycles. | |||||||||||||||
20 | SMC_TDFEN AT91C_SMC_TDFEN | TDF Enabled. 0: TDF optimisation is disabled. 1: TDF optimisation is enabled. | |||||||||||||||
24 | SMC_PMEN AT91C_SMC_PMEN | Page Mode Enabled. 0: Page Mode is disabled. 1: Page Mode is enabled. | |||||||||||||||
29..28 | SMC_PS AT91C_SMC_PS | Page Size 0: 4 bytes. 1: 8 bytes. 2: 16 bytes. 3: 32 bytes.
|