AHB Matrix Interface Peripheral

MATRIX (AT91S_MATRIX) 0xFFFFEE00 (AT91C_BASE_MATRIX)

MATRIX Software API (AT91S_MATRIX)

OffsetFieldDescription
0x0MATRIX_MCFG Master Configuration Register
0x4MATRIX_SCFG0 Slave Configuration Register 0
0x8MATRIX_SCFG1 Slave Configuration Register 1
0xCMATRIX_SCFG2 Slave Configuration Register 2
0x10MATRIX_SCFG3 Slave Configuration Register 3
0x14MATRIX_SCFG4 Slave Configuration Register 4
0x24MATRIX_TCMR Slave 0 Special Function Register
0x30MATRIX_EBICSA Slave 3 Special Function Register
0x34MATRIX_USBPCR Slave 4 Special Function Register
0x44MATRIX_VERSION Version Register

FunctionDescription
AT91F_MATRIX_DisableSM_On_CS3Disable the Chip Select 3 for CF Controller
AT91F_MATRIX_EnableSDRAMCEnable the Chip Select of the SDRAM Controller
AT91F_MATRIX_Remap_ARMIEnable Remap of ARM-I
AT91F_MATRIX_EnableSM_On_CS3Enable the Chip Select 3 for CF Controller
AT91F_MATRIX_Disable_Remap_ARMIDisable Remap of ARM-I
AT91F_MATRIX_DisableEBIPULLUPDisable the EBI PULLUP
AT91F_MATRIX_DisableSDRAMCDisable the Chip Select of the SDRAM Controller
AT91F_MATRIX_DisableCF_On_CS4Disable the Chip Select 4 for CF Controller
AT91F_MATRIX_Disable_Remap_ARMDisable Remap of ARM
AT91F_MATRIX_Disable_Remap_ARM-DDisable Remap of ARM-D
AT91F_MATRIX_DisableCF_On_CS5Disable the Chip Select 5 for CF Controller
AT91F_MATRIX_Set_TCM_SizeEnable one or more TCM block
AT91F_MATRIX_EnableEBIPULLUPEnable the EBI PULLUP
AT91F_MATRIX_Remap_ARMEnable Remap of ARM
AT91F_MATRIX_EnableCF_On_CS4Enable the Chip Select 4 for CF Controller
AT91F_MATRIX_EnableCF_On_CS5Enable the Chip Select 5 for CF Controller
AT91F_MATRIX_Remap_ARMDEnable Remap of ARM-D

MATRIX Register Description

MATRIX: AT91_REG MATRIX_MCFG Master Configuration Register

OffsetNameDescription
0MATRIX_RCA926I
AT91C_MATRIX_RCA926I
Remap Command for ARM926EJ-S Instruction Master
0: No Effect
1: This command bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x
1MATRIX_RCA926D
AT91C_MATRIX_RCA926D
Remap Command for ARM926EJ-S Data Master
0: No Effect
1: This command bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x

MATRIX: AT91_REG MATRIX_SCFG0 Slave Configuration Register 0

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
20..18MATRIX_FIXED_DEFMSTR0
AT91C_MATRIX_FIXED_DEFMSTR0
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR0_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR0_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR0_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3

HPDC3 Master is Default Master
3MATRIX_FIXED_DEFMSTR0_LCDC
AT91C_MATRIX_FIXED_DEFMSTR0_LCDC

LCDC Master is Default Master
4MATRIX_FIXED_DEFMSTR0_UHP
AT91C_MATRIX_FIXED_DEFMSTR0_UHP

UHP Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG1 Slave Configuration Register 1

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
20..18MATRIX_FIXED_DEFMSTR1
AT91C_MATRIX_FIXED_DEFMSTR1
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR1_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR1_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR1_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3

HPDC3 Master is Default Master
3MATRIX_FIXED_DEFMSTR1_LCDC
AT91C_MATRIX_FIXED_DEFMSTR1_LCDC

LCDC Master is Default Master
4MATRIX_FIXED_DEFMSTR1_UHP
AT91C_MATRIX_FIXED_DEFMSTR1_UHP

UHP Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG2 Slave Configuration Register 2

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
18MATRIX_FIXED_DEFMSTR2
AT91C_MATRIX_FIXED_DEFMSTR2
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR2_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR2_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D

ARM926EJ-S Data Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG3 Slave Configuration Register 3

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
20..18MATRIX_FIXED_DEFMSTR3
AT91C_MATRIX_FIXED_DEFMSTR3
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR3_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR3_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR3_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3

HPDC3 Master is Default Master
3MATRIX_FIXED_DEFMSTR3_LCDC
AT91C_MATRIX_FIXED_DEFMSTR3_LCDC

LCDC Master is Default Master
4MATRIX_FIXED_DEFMSTR3_UHP
AT91C_MATRIX_FIXED_DEFMSTR3_UHP

UHP Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG4 Slave Configuration Register 4

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
19..18MATRIX_FIXED_DEFMSTR4
AT91C_MATRIX_FIXED_DEFMSTR4
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR4_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR4_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR4_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3

HPDC3 Master is Default Master

MATRIX: AT91_REG MATRIX_TCMR Slave 0 Special Function Register

OffsetNameDescription
3..0MATRIX_ITCM_SIZE
AT91C_MATRIX_ITCM_SIZE
Size of ITCM enabled memory block
ValueLabelDescription
0MATRIX_ITCM_SIZE_0KB
AT91C_MATRIX_ITCM_SIZE_0KB

0 KB (No ITCM Memory)
5MATRIX_ITCM_SIZE_16KB
AT91C_MATRIX_ITCM_SIZE_16KB

16 KB
6MATRIX_ITCM_SIZE_32KB
AT91C_MATRIX_ITCM_SIZE_32KB

32 KB
7MATRIX_ITCM_SIZE_64KB
AT91C_MATRIX_ITCM_SIZE_64KB

64 KB
7..4MATRIX_DTCM_SIZE
AT91C_MATRIX_DTCM_SIZE
Size of DTCM enabled memory block
ValueLabelDescription
0MATRIX_DTCM_SIZE_0KB
AT91C_MATRIX_DTCM_SIZE_0KB

0 KB (No DTCM Memory)
5MATRIX_DTCM_SIZE_16KB
AT91C_MATRIX_DTCM_SIZE_16KB

16 KB
6MATRIX_DTCM_SIZE_32KB
AT91C_MATRIX_DTCM_SIZE_32KB

32 KB
7MATRIX_DTCM_SIZE_64KB
AT91C_MATRIX_DTCM_SIZE_64KB

64 KB

MATRIX: AT91_REG MATRIX_EBICSA Slave 3 Special Function Register

OffsetNameDescription
1MATRIX_CS1A
AT91C_MATRIX_CS1A
Chip Select 1 Assignment
0: Chip Select 1 is assigned to the Static Memory Controller.
1: Chip Select 1 is assigned to the SDRAM Controller.
ValueLabelDescription
0MATRIX_CS1A_SMC
AT91C_MATRIX_CS1A_SMC

Chip Select 1 is assigned to the Static Memory Controller.
1MATRIX_CS1A_SDRAMC
AT91C_MATRIX_CS1A_SDRAMC

Chip Select 1 is assigned to the SDRAM Controller.
3MATRIX_CS3A
AT91C_MATRIX_CS3A
Chip Select 3 Assignment
0: Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
1: Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
ValueLabelDescription
0MATRIX_CS3A_SMC
AT91C_MATRIX_CS3A_SMC

Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
1MATRIX_CS3A_SM
AT91C_MATRIX_CS3A_SM

Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
4MATRIX_CS4A
AT91C_MATRIX_CS4A
Chip Select 4 Assignment
0: Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
1: Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
ValueLabelDescription
0MATRIX_CS4A_SMC
AT91C_MATRIX_CS4A_SMC

Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
1MATRIX_CS4A_CF
AT91C_MATRIX_CS4A_CF

Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
5MATRIX_CS5A
AT91C_MATRIX_CS5A
Chip Select 5 Assignment
0: Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC.
1: Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
ValueLabelDescription
0MATRIX_CS5A_SMC
AT91C_MATRIX_CS5A_SMC

Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
1MATRIX_CS5A_CF
AT91C_MATRIX_CS5A_CF

Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
8MATRIX_DBPUC
AT91C_MATRIX_DBPUC
Data Bus Pull-up Configuration
0: D0-D15 Data Bus bits are internally pulled-up to the VDDIOM power supply.
1: D0-D15 Data Bus bits are not internally pulled-up.

MATRIX: AT91_REG MATRIX_USBPCR Slave 4 Special Function Register

OffsetNameDescription
30MATRIX_USBPCR_PUON
AT91C_MATRIX_USBPCR_PUON
PullUp On
31MATRIX_USBPCR_PUIDLE
AT91C_MATRIX_USBPCR_PUIDLE
PullUp Idle

MATRIX: AT91_REG MATRIX_VERSION Version Register