Clock Generator Controler Peripheral

CKGR (AT91S_CKGR) 0xFFFFFC20 (AT91C_BASE_CKGR)

CKGR Software API (AT91S_CKGR)

OffsetFieldDescription
0x0CKGR_MORMain Oscillator Register
0x4CKGR_MCFRMain Clock Frequency Register
0x8CKGR_PLLARPLL A Register
0xCCKGR_PLLBRPLL B Register

CKGR Register Description

CKGR: AT91_REG CKGR_MOR Main Oscillator Register

OffsetNameDescription
0CKGR_MOSCEN
AT91C_CKGR_MOSCEN
Main Oscillator Enable
0 = The main oscillator is disabled.
1 = The main oscillator is enabled. OSCBYPASS must be set to 0.
1CKGR_OSCBYPASS
AT91C_CKGR_OSCBYPASS
Main Oscillator Bypass
0 = The main oscillator is not bypassed.
1 = The main oscillator is bypassed. MOSCEN bit must be set to 0.
15..8CKGR_OSCOUNT
AT91C_CKGR_OSCOUNT
Main Oscillator Start-up Time
Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.

CKGR: AT91_REG CKGR_MCFR Main Clock Frequency Register

OffsetNameDescription
15..0CKGR_MAINF
AT91C_CKGR_MAINF
Main Clock Frequency
Gives the number of main clock cycles within 16 slow clock periods.
16CKGR_MAINRDY
AT91C_CKGR_MAINRDY
Main Clock Ready
0 = FMAIN value is not valid or the main oscillator is disabled.
1 = The main oscillator has been enabled previously and MAINF value is available.

CKGR: AT91_REG CKGR_PLLAR PLL A Register

OffsetNameDescription
7..0CKGR_DIVA
AT91C_CKGR_DIVA
Divider A Selected
2-255 Divider output is the selected clock divided by DIVA
ValueLabelDescription
0CKGR_DIVA_0
AT91C_CKGR_DIVA_0

Divider A output is 0
1CKGR_DIVA_BYPASS
AT91C_CKGR_DIVA_BYPASS

Divider A is bypassed
13..8CKGR_PLLACOUNT
AT91C_CKGR_PLLACOUNT
PLL A Counter
Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after PMC_PLLA is written.
15..14CKGR_OUTA
AT91C_CKGR_OUTA
PLL A Output Frequency Range
ValueLabelDescription
0CKGR_OUTA_0
AT91C_CKGR_OUTA_0

Please refer to the PLLA datasheet
1CKGR_OUTA_1
AT91C_CKGR_OUTA_1

Please refer to the PLLA datasheet
2CKGR_OUTA_2
AT91C_CKGR_OUTA_2

Please refer to the PLLA datasheet
3CKGR_OUTA_3
AT91C_CKGR_OUTA_3

Please refer to the PLLA datasheet
26..16CKGR_MULA
AT91C_CKGR_MULA
PLL A Multiplier
0 = The PLL A is deactivated.
1 up to 2047 = The PLL A output frequency is the PLL A input frequency multiplied by MULA + 1.
29CKGR_SRCA
AT91C_CKGR_SRCA

BE CAREFUL !!! This bit MUST BE SET TO 1.

CKGR: AT91_REG CKGR_PLLBR PLL B Register

OffsetNameDescription
7..0CKGR_DIVB
AT91C_CKGR_DIVB
Divider B Selected
2-255 Divider output is the selected clock divided by DIVB
ValueLabelDescription
0CKGR_DIVB_0
AT91C_CKGR_DIVB_0

Divider B output is 0
1CKGR_DIVB_BYPASS
AT91C_CKGR_DIVB_BYPASS

Divider B is bypassed
13..8CKGR_PLLBCOUNT
AT91C_CKGR_PLLBCOUNT
PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after PMC_PLLB is written.
15..14CKGR_OUTB
AT91C_CKGR_OUTB
PLL B Output Frequency Range
ValueLabelDescription
0CKGR_OUTB_0
AT91C_CKGR_OUTB_0

Please refer to the PLLB datasheet
1CKGR_OUTB_1
AT91C_CKGR_OUTB_1

Please refer to the PLLB datasheet
2CKGR_OUTB_2
AT91C_CKGR_OUTB_2

Please refer to the PLLB datasheet
3CKGR_OUTB_3
AT91C_CKGR_OUTB_3

Please refer to the PLLB datasheet
26..16CKGR_MULB
AT91C_CKGR_MULB
PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 2047 = The PLL B output frequency is the PLL B input frequency multiplied by MULB + 1.
29..28CKGR_USBDIV
AT91C_CKGR_USBDIV
Divider for USB Clocks
ValueLabelDescription
0CKGR_USBDIV_0
AT91C_CKGR_USBDIV_0

Divider output is PLL clock output
1CKGR_USBDIV_1
AT91C_CKGR_USBDIV_1

Divider output is PLL clock output divided by 2
2CKGR_USBDIV_2
AT91C_CKGR_USBDIV_2

Divider output is PLL clock output divided by 4