Offset | Field | Description |
---|---|---|
0x0 | CKGR_MOR | Main Oscillator Register |
0x4 | CKGR_MCFR | Main Clock Frequency Register |
0x8 | CKGR_PLLAR | PLL A Register |
0xC | CKGR_PLLBR | PLL B Register |
Offset | Name | Description |
---|---|---|
0 | CKGR_MOSCEN AT91C_CKGR_MOSCEN | Main Oscillator Enable 0 = The main oscillator is disabled. 1 = The main oscillator is enabled. OSCBYPASS must be set to 0. |
1 | CKGR_OSCBYPASS AT91C_CKGR_OSCBYPASS | Main Oscillator Bypass 0 = The main oscillator is not bypassed. 1 = The main oscillator is bypassed. MOSCEN bit must be set to 0. |
15..8 | CKGR_OSCOUNT AT91C_CKGR_OSCOUNT | Main Oscillator Start-up Time Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time. |
Offset | Name | Description |
---|---|---|
15..0 | CKGR_MAINF AT91C_CKGR_MAINF | Main Clock Frequency Gives the number of main clock cycles within 16 slow clock periods. |
16 | CKGR_MAINRDY AT91C_CKGR_MAINRDY | Main Clock Ready 0 = FMAIN value is not valid or the main oscillator is disabled. 1 = The main oscillator has been enabled previously and MAINF value is available. |
Offset | Name | Description | |||||||||||||||
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7..0 | CKGR_DIVA AT91C_CKGR_DIVA | Divider A Selected 2-255 Divider output is the selected clock divided by DIVA
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13..8 | CKGR_PLLACOUNT AT91C_CKGR_PLLACOUNT | PLL A Counter Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after PMC_PLLA is written. | |||||||||||||||
15..14 | CKGR_OUTA AT91C_CKGR_OUTA | PLL A Output Frequency Range
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26..16 | CKGR_MULA AT91C_CKGR_MULA | PLL A Multiplier 0 = The PLL A is deactivated. 1 up to 2047 = The PLL A output frequency is the PLL A input frequency multiplied by MULA + 1. | |||||||||||||||
29 | CKGR_SRCA AT91C_CKGR_SRCA | BE CAREFUL !!! This bit MUST BE SET TO 1. |
Offset | Name | Description | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
7..0 | CKGR_DIVB AT91C_CKGR_DIVB | Divider B Selected 2-255 Divider output is the selected clock divided by DIVB
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13..8 | CKGR_PLLBCOUNT AT91C_CKGR_PLLBCOUNT | PLL B Counter Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after PMC_PLLB is written. | |||||||||||||||
15..14 | CKGR_OUTB AT91C_CKGR_OUTB | PLL B Output Frequency Range
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26..16 | CKGR_MULB AT91C_CKGR_MULB | PLL B Multiplier 0 = The PLL B is deactivated. 1 up to 2047 = The PLL B output frequency is the PLL B input frequency multiplied by MULB + 1. | |||||||||||||||
29..28 | CKGR_USBDIV AT91C_CKGR_USBDIV | Divider for USB Clocks
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