DMA controller from Synopsys Peripheral

DMA (AT91S_DMA) 0x00800000 (AT91C_BASE_DMA)
Periph ID AICSymbolDescription
27 (AT91C_ID_DMA)DMA Controller

FunctionDescription
AT91F_DMA_CfgPMCEnable Peripheral clock in PMC for DMA


DMA Software API (AT91S_DMA)

OffsetFieldDescription
0x0DMA_SAR0 (DMA_SAR)Source Address Register for channel 0
0x8DMA_DAR0 (DMA_DAR)Destination Address Register for channel 0
0x10DMA_LLP0 (DMA_LLP)Linked List Pointer Register for channel 0
0x18DMA_CTL0l (DMA_CTLl)Control Register for channel 0 - low
0x1CDMA_CTL0h (DMA_CTLh)Control Register for channel 0 - high
0x20DMA_SSTAT0 (DMA_SSTAT)Source Status Register for channel 0
0x28DMA_DSTAT0 (DMA_DSTAT)Destination Status Register for channel 0
0x30DMA_SSTATAR0 (DMA_SSTATAR)Source Status Adress Register for channel 0
0x38DMA_DSTATAR0 (DMA_DSTATAR)Destination Status Adress Register for channel 0
0x40DMA_CFG0l (DMA_CFGl)Configuration Register for channel 0 - low
0x44DMA_CFG0h (DMA_CFGh)Configuration Register for channel 0 - high
0x48DMA_SGR0 (DMA_SGR)Source Gather Register for channel 0
0x50DMA_DSR0 (DMA_DSR)Destination Scatter Register for channel 0
0x58DMA_SAR1 (DMA_SAR)Source Address Register for channel 1
0x60DMA_DAR1 (DMA_DAR)Destination Address Register for channel 1
0x68DMA_LLP1 (DMA_LLP)Linked List Pointer Register for channel 1
0x70DMA_CTL1l (DMA_CTLl)Control Register for channel 1 - low
0x74DMA_CTL1h (DMA_CTLh)Control Register for channel 1 - high
0x78DMA_SSTAT1 (DMA_SSTAT)Source Status Register for channel 1
0x80DMA_DSTAT1 (DMA_DSTAT)Destination Status Register for channel 1
0x88DMA_SSTATAR1 (DMA_SSTATAR)Source Status Adress Register for channel 1
0x90DMA_DSTATAR1 (DMA_DSTATAR)Destination Status Adress Register for channel 1
0x98DMA_CFG1l (DMA_CFGl)Configuration Register for channel 1 - low
0x9CDMA_CFG1h (DMA_CFGh)Configuration Register for channel 1 - high
0xA0DMA_SGR1 (DMA_SGR)Source Gather Register for channel 1
0xA8DMA_DSR1 (DMA_DSR)Destination Scatter Register for channel 1
0x2C0DMA_RAWTFRRaw Status for IntTfr Interrupt
0x2C8DMA_RAWBLOCKRaw Status for IntBlock Interrupt
0x2D0DMA_RAWSRCTRANRaw Status for IntSrcTran Interrupt
0x2D8DMA_RAWDSTTRANRaw Status for IntDstTran Interrupt
0x2E0DMA_RAWERRRaw Status for IntErr Interrupt
0x2E8DMA_STATUSTFRStatus for IntTfr Interrupt
0x2F0DMA_STATUSBLOCKStatus for IntBlock Interrupt
0x2F8DMA_STATUSSRCTRANStatus for IntSrcTran Interrupt
0x300DMA_STATUSDSTTRANStatus for IntDstTran IInterrupt
0x308DMA_STATUSERRStatus for IntErr IInterrupt
0x310DMA_MASKTFRMask for IntTfr Interrupt
0x318DMA_MASKBLOCKMask for IntBlock Interrupt
0x320DMA_MASKSRCTRANMask for IntSrcTran Interrupt
0x328DMA_MASKDSTTRANMask for IntDstTran Interrupt
0x330DMA_MASKERRMask for IntErr Interrupt
0x338DMA_CLEARTFRClear for IntTfr Interrupt
0x340DMA_CLEARBLOCKClear for IntBlock Interrupt
0x348DMA_CLEARSRCTRANClear for IntSrcTran Interrupt
0x350DMA_CLEARDSTTRANClear for IntDstTran IInterrupt
0x358DMA_CLEARERRClear for IntErr Interrupt
0x360DMA_STATUSINTStatus for each Interrupt Type
0x368DMA_REQSRCREGSource Software Transaction Request Register
0x370DMA_REQDSTREGDestination Software Transaction Request Register
0x378DMA_SGLREQSRCREGSingle Source Software Transaction Request Register
0x380DMA_SGLREQDSTREGSingle Destination Software Transaction Request Register
0x388DMA_LSTREQSRCREGLast Source Software Transaction Request Register
0x390DMA_LSTREQDSTREGLast Destination Software Transaction Request Register
0x398DMA_DMACFGREGDW_ahb_dmac Configuration Register
0x3A0DMA_CHENREGDW_ahb_dmac Channel Enable Register
0x3A8DMA_DMAIDREGDW_ahb_dmac ID Register
0x3B0DMA_DMATESTREGDW_ahb_dmac Test Register
0x3B8DMA_VERSIONIDDW_ahb_dmac Version ID Register

FunctionDescription
AT91F_DMA_EnableEnable the DMA controller

DMA Register Description

DMA: AT91_REG DMA_SAR0 Source Address Register for channel 0

OffsetNameDescription
31..0DMA_SADD
AT91C_DMA_SADD
Source Address of DMA Transfer

DMA: AT91_REG DMA_DAR0 Destination Address Register for channel 0

OffsetNameDescription
31..0DMA_DADD
AT91C_DMA_DADD
Destination Address of DMA Transfer

DMA: AT91_REG DMA_LLP0 Linked List Pointer Register for channel 0

OffsetNameDescription
31..0DMA_LOC
AT91C_DMA_LOC
Address of the Next LLI

DMA: AT91_REG DMA_CTL0l Control Register for channel 0 - low

OffsetNameDescription
0DMA_INT_EN
AT91C_DMA_INT_EN
Interrupt Enable Bit
3..1DMA_DST_TR_WIDTH
AT91C_DMA_DST_TR_WIDTH
Destination Transfer Width
6..4DMA_SRC_TR_WIDTH
AT91C_DMA_SRC_TR_WIDTH
Source Transfer Width
8..7DMA_DINC
AT91C_DMA_DINC
Destination Address Increment
10..9DMA_SINC
AT91C_DMA_SINC
Source Address Increment
13..11DMA_DEST_MSIZE
AT91C_DMA_DEST_MSIZE
Destination Burst Transaction Length
16..14DMA_SRC_MSIZE
AT91C_DMA_SRC_MSIZE
Source Burst Transaction Length
17DMA_S_GATH_EN
AT91C_DMA_S_GATH_EN
Source Gather Enable Bit
18DMA_D_SCAT_EN
AT91C_DMA_D_SCAT_EN
Destination Scatter Enable Bit
22..20DMA_TT_FC
AT91C_DMA_TT_FC
Transfer Type and Flow Control
24..23DMA_DMS
AT91C_DMA_DMS
Destination Master Select
26..25DMA_SMS
AT91C_DMA_SMS
Source Master Select
27DMA_LLP_D_EN
AT91C_DMA_LLP_D_EN
Destination Block Chaining Enable
28DMA_LLP_S_EN
AT91C_DMA_LLP_S_EN
Source Block Chaining Enable

DMA: AT91_REG DMA_CTL0h Control Register for channel 0 - high

OffsetNameDescription
11..0DMA_BLOCK_TS
AT91C_DMA_BLOCK_TS
Block Transfer Size
12DMA_DONE
AT91C_DMA_DONE
Done bit

DMA: AT91_REG DMA_SSTAT0 Source Status Register for channel 0


Source Status Information

DMA: AT91_REG DMA_DSTAT0 Destination Status Register for channel 0


Destination Status Information

DMA: AT91_REG DMA_SSTATAR0 Source Status Adress Register for channel 0


Source Status Information Address

DMA: AT91_REG DMA_DSTATAR0 Destination Status Adress Register for channel 0


Destination Status Information Address

DMA: AT91_REG DMA_CFG0l Configuration Register for channel 0 - low

OffsetNameDescription
7..5DMA_CH_PRIOR
AT91C_DMA_CH_PRIOR
Channel Priority
8DMA_CH_SUSP
AT91C_DMA_CH_SUSP
Channel Suspend
9DMA_FIFO_EMPT
AT91C_DMA_FIFO_EMPT
Fifo Empty
10DMA_HS_SEL_DS
AT91C_DMA_HS_SEL_DS
Destination Software or Hardware Handshaking Select
11DMA_HS_SEL_SR
AT91C_DMA_HS_SEL_SR
Source Software or Hardware Handshaking Select
13..12DMA_LOCK_CH_L
AT91C_DMA_LOCK_CH_L
Channel Lock Level
15..14DMA_LOCK_B_L
AT91C_DMA_LOCK_B_L
Bus Lock Level
16DMA_LOCK_CH
AT91C_DMA_LOCK_CH
Channel Lock Bit
17DMA_LOCK_B
AT91C_DMA_LOCK_B
Bus Lock Bit
18DMA_DS_HS_POL
AT91C_DMA_DS_HS_POL
Destination Handshaking Interface Polarity
19DMA_SR_HS_POL
AT91C_DMA_SR_HS_POL
Source Handshaking Interface Polarity
29..20DMA_MAX_ABRST
AT91C_DMA_MAX_ABRST
Maximum AMBA Burst Length
30DMA_RELOAD_SR
AT91C_DMA_RELOAD_SR
Automatic Source Reload
31DMA_RELOAD_DS
AT91C_DMA_RELOAD_DS
Automatic Destination Reload

DMA: AT91_REG DMA_CFG0h Configuration Register for channel 0 - high

OffsetNameDescription
0DMA_FCMODE
AT91C_DMA_FCMODE
Flow Control Mode
1DMA_FIFO_MODE
AT91C_DMA_FIFO_MODE
Fifo Mode Select
4..2DMA_PROTCTL
AT91C_DMA_PROTCTL
Protection Control
5DMA_DS_UPD_EN
AT91C_DMA_DS_UPD_EN
Destination Status Update Enable
6DMA_SS_UPD_EN
AT91C_DMA_SS_UPD_EN
Source Status Update Enable
10..7DMA_SRC_PER
AT91C_DMA_SRC_PER
Source Hardware Handshaking Interface
Assigns a h/w handshaking interface (0-DMAH_NUM_HS_INT-1) to the source of channel X if CFGx.HS_SEL_DST field is 0
14..11DMA_DEST_PER
AT91C_DMA_DEST_PER
Destination Hardware Handshaking Interface

DMA: AT91_REG DMA_SGR0 Source Gather Register for channel 0

OffsetNameDescription
19..0DMA_SGI
AT91C_DMA_SGI
Source Gather Interval
31..20DMA_SGC
AT91C_DMA_SGC
Source Gather Count

DMA: AT91_REG DMA_DSR0 Destination Scatter Register for channel 0

OffsetNameDescription
19..0DMA_DSI
AT91C_DMA_DSI
Destination Scatter Interval
31..20DMA_DSC
AT91C_DMA_DSC
Destination Scatter Count

DMA: AT91_REG DMA_SAR1 Source Address Register for channel 1

OffsetNameDescription
31..0DMA_SADD
AT91C_DMA_SADD
Source Address of DMA Transfer

DMA: AT91_REG DMA_DAR1 Destination Address Register for channel 1

OffsetNameDescription
31..0DMA_DADD
AT91C_DMA_DADD
Destination Address of DMA Transfer

DMA: AT91_REG DMA_LLP1 Linked List Pointer Register for channel 1

OffsetNameDescription
31..0DMA_LOC
AT91C_DMA_LOC
Address of the Next LLI

DMA: AT91_REG DMA_CTL1l Control Register for channel 1 - low

OffsetNameDescription
0DMA_INT_EN
AT91C_DMA_INT_EN
Interrupt Enable Bit
3..1DMA_DST_TR_WIDTH
AT91C_DMA_DST_TR_WIDTH
Destination Transfer Width
6..4DMA_SRC_TR_WIDTH
AT91C_DMA_SRC_TR_WIDTH
Source Transfer Width
8..7DMA_DINC
AT91C_DMA_DINC
Destination Address Increment
10..9DMA_SINC
AT91C_DMA_SINC
Source Address Increment
13..11DMA_DEST_MSIZE
AT91C_DMA_DEST_MSIZE
Destination Burst Transaction Length
16..14DMA_SRC_MSIZE
AT91C_DMA_SRC_MSIZE
Source Burst Transaction Length
17DMA_S_GATH_EN
AT91C_DMA_S_GATH_EN
Source Gather Enable Bit
18DMA_D_SCAT_EN
AT91C_DMA_D_SCAT_EN
Destination Scatter Enable Bit
22..20DMA_TT_FC
AT91C_DMA_TT_FC
Transfer Type and Flow Control
24..23DMA_DMS
AT91C_DMA_DMS
Destination Master Select
26..25DMA_SMS
AT91C_DMA_SMS
Source Master Select
27DMA_LLP_D_EN
AT91C_DMA_LLP_D_EN
Destination Block Chaining Enable
28DMA_LLP_S_EN
AT91C_DMA_LLP_S_EN
Source Block Chaining Enable

DMA: AT91_REG DMA_CTL1h Control Register for channel 1 - high

OffsetNameDescription
11..0DMA_BLOCK_TS
AT91C_DMA_BLOCK_TS
Block Transfer Size
12DMA_DONE
AT91C_DMA_DONE
Done bit

DMA: AT91_REG DMA_SSTAT1 Source Status Register for channel 1


Source Status Information

DMA: AT91_REG DMA_DSTAT1 Destination Status Register for channel 1


Destination Status Information

DMA: AT91_REG DMA_SSTATAR1 Source Status Adress Register for channel 1


Source Status Information Address

DMA: AT91_REG DMA_DSTATAR1 Destination Status Adress Register for channel 1


Destination Status Information Address

DMA: AT91_REG DMA_CFG1l Configuration Register for channel 1 - low

OffsetNameDescription
7..5DMA_CH_PRIOR
AT91C_DMA_CH_PRIOR
Channel Priority
8DMA_CH_SUSP
AT91C_DMA_CH_SUSP
Channel Suspend
9DMA_FIFO_EMPT
AT91C_DMA_FIFO_EMPT
Fifo Empty
10DMA_HS_SEL_DS
AT91C_DMA_HS_SEL_DS
Destination Software or Hardware Handshaking Select
11DMA_HS_SEL_SR
AT91C_DMA_HS_SEL_SR
Source Software or Hardware Handshaking Select
13..12DMA_LOCK_CH_L
AT91C_DMA_LOCK_CH_L
Channel Lock Level
15..14DMA_LOCK_B_L
AT91C_DMA_LOCK_B_L
Bus Lock Level
16DMA_LOCK_CH
AT91C_DMA_LOCK_CH
Channel Lock Bit
17DMA_LOCK_B
AT91C_DMA_LOCK_B
Bus Lock Bit
18DMA_DS_HS_POL
AT91C_DMA_DS_HS_POL
Destination Handshaking Interface Polarity
19DMA_SR_HS_POL
AT91C_DMA_SR_HS_POL
Source Handshaking Interface Polarity
29..20DMA_MAX_ABRST
AT91C_DMA_MAX_ABRST
Maximum AMBA Burst Length
30DMA_RELOAD_SR
AT91C_DMA_RELOAD_SR
Automatic Source Reload
31DMA_RELOAD_DS
AT91C_DMA_RELOAD_DS
Automatic Destination Reload

DMA: AT91_REG DMA_CFG1h Configuration Register for channel 1 - high

OffsetNameDescription
0DMA_FCMODE
AT91C_DMA_FCMODE
Flow Control Mode
1DMA_FIFO_MODE
AT91C_DMA_FIFO_MODE
Fifo Mode Select
4..2DMA_PROTCTL
AT91C_DMA_PROTCTL
Protection Control
5DMA_DS_UPD_EN
AT91C_DMA_DS_UPD_EN
Destination Status Update Enable
6DMA_SS_UPD_EN
AT91C_DMA_SS_UPD_EN
Source Status Update Enable
10..7DMA_SRC_PER
AT91C_DMA_SRC_PER
Source Hardware Handshaking Interface
Assigns a h/w handshaking interface (0-DMAH_NUM_HS_INT-1) to the source of channel X if CFGx.HS_SEL_DST field is 0
14..11DMA_DEST_PER
AT91C_DMA_DEST_PER
Destination Hardware Handshaking Interface

DMA: AT91_REG DMA_SGR1 Source Gather Register for channel 1

OffsetNameDescription
19..0DMA_SGI
AT91C_DMA_SGI
Source Gather Interval
31..20DMA_SGC
AT91C_DMA_SGC
Source Gather Count

DMA: AT91_REG DMA_DSR1 Destination Scatter Register for channel 1

OffsetNameDescription
19..0DMA_DSI
AT91C_DMA_DSI
Destination Scatter Interval
31..20DMA_DSC
AT91C_DMA_DSC
Destination Scatter Count

DMA: AT91_REG DMA_RAWTFR Raw Status for IntTfr Interrupt

OffsetNameDescription
2..0DMA_RAW
AT91C_DMA_RAW
Raw Interrupt for each Channel

DMA: AT91_REG DMA_RAWBLOCK Raw Status for IntBlock Interrupt

OffsetNameDescription
2..0DMA_RAW
AT91C_DMA_RAW
Raw Interrupt for each Channel

DMA: AT91_REG DMA_RAWSRCTRAN Raw Status for IntSrcTran Interrupt

OffsetNameDescription
2..0DMA_RAW
AT91C_DMA_RAW
Raw Interrupt for each Channel

DMA: AT91_REG DMA_RAWDSTTRAN Raw Status for IntDstTran Interrupt

OffsetNameDescription
2..0DMA_RAW
AT91C_DMA_RAW
Raw Interrupt for each Channel

DMA: AT91_REG DMA_RAWERR Raw Status for IntErr Interrupt

OffsetNameDescription
2..0DMA_RAW
AT91C_DMA_RAW
Raw Interrupt for each Channel

DMA: AT91_REG DMA_STATUSTFR Status for IntTfr Interrupt

OffsetNameDescription
2..0DMA_STATUS
AT91C_DMA_STATUS
Interrupt for each Channel

DMA: AT91_REG DMA_STATUSBLOCK Status for IntBlock Interrupt

OffsetNameDescription
2..0DMA_STATUS
AT91C_DMA_STATUS
Interrupt for each Channel

DMA: AT91_REG DMA_STATUSSRCTRAN Status for IntSrcTran Interrupt

OffsetNameDescription
2..0DMA_STATUS
AT91C_DMA_STATUS
Interrupt for each Channel

DMA: AT91_REG DMA_STATUSDSTTRAN Status for IntDstTran IInterrupt

OffsetNameDescription
2..0DMA_STATUS
AT91C_DMA_STATUS
Interrupt for each Channel

DMA: AT91_REG DMA_STATUSERR Status for IntErr IInterrupt

OffsetNameDescription
2..0DMA_RAW
AT91C_DMA_RAW
Raw Interrupt for each Channel

DMA: AT91_REG DMA_MASKTFR Mask for IntTfr Interrupt

OffsetNameDescription
2..0DMA_INT_MASK
AT91C_DMA_INT_MASK
Interrupt Mask for each Channel
10..8DMA_INT_M_WE
AT91C_DMA_INT_M_WE
Interrupt Mask Write Enable for each Channel

DMA: AT91_REG DMA_MASKBLOCK Mask for IntBlock Interrupt

OffsetNameDescription
2..0DMA_INT_MASK
AT91C_DMA_INT_MASK
Interrupt Mask for each Channel
10..8DMA_INT_M_WE
AT91C_DMA_INT_M_WE
Interrupt Mask Write Enable for each Channel

DMA: AT91_REG DMA_MASKSRCTRAN Mask for IntSrcTran Interrupt

OffsetNameDescription
2..0DMA_INT_MASK
AT91C_DMA_INT_MASK
Interrupt Mask for each Channel
10..8DMA_INT_M_WE
AT91C_DMA_INT_M_WE
Interrupt Mask Write Enable for each Channel

DMA: AT91_REG DMA_MASKDSTTRAN Mask for IntDstTran Interrupt

OffsetNameDescription
2..0DMA_INT_MASK
AT91C_DMA_INT_MASK
Interrupt Mask for each Channel
10..8DMA_INT_M_WE
AT91C_DMA_INT_M_WE
Interrupt Mask Write Enable for each Channel

DMA: AT91_REG DMA_MASKERR Mask for IntErr Interrupt

OffsetNameDescription
2..0DMA_INT_MASK
AT91C_DMA_INT_MASK
Interrupt Mask for each Channel
10..8DMA_INT_M_WE
AT91C_DMA_INT_M_WE
Interrupt Mask Write Enable for each Channel

DMA: AT91_REG DMA_CLEARTFR Clear for IntTfr Interrupt

OffsetNameDescription
2..0DMA_CLEAR
AT91C_DMA_CLEAR
Interrupt Clear for each Channel

DMA: AT91_REG DMA_CLEARBLOCK Clear for IntBlock Interrupt

OffsetNameDescription
2..0DMA_CLEAR
AT91C_DMA_CLEAR
Interrupt Clear for each Channel

DMA: AT91_REG DMA_CLEARSRCTRAN Clear for IntSrcTran Interrupt

OffsetNameDescription
2..0DMA_CLEAR
AT91C_DMA_CLEAR
Interrupt Clear for each Channel

DMA: AT91_REG DMA_CLEARDSTTRAN Clear for IntDstTran IInterrupt

OffsetNameDescription
2..0DMA_CLEAR
AT91C_DMA_CLEAR
Interrupt Clear for each Channel

DMA: AT91_REG DMA_CLEARERR Clear for IntErr Interrupt

OffsetNameDescription
2..0DMA_CLEAR
AT91C_DMA_CLEAR
Interrupt Clear for each Channel

DMA: AT91_REG DMA_STATUSINT Status for each Interrupt Type

OffsetNameDescription
0DMA_TFR
AT91C_DMA_TFR
OR of the content of StatusTfr Register
1DMA_BLOCK
AT91C_DMA_BLOCK
OR of the content of StatusBlock Register
2DMA_SRCT
AT91C_DMA_SRCT
OR of the content of StatusSrcTran Register
3DMA_DSTT
AT91C_DMA_DSTT
OR of the content of StatusDstTran Register
4DMA_ERR
AT91C_DMA_ERR
OR of the content of StatusErr Register

DMA: AT91_REG DMA_REQSRCREG Source Software Transaction Request Register

OffsetNameDescription
2..0DMA_SRC_REQ
AT91C_DMA_SRC_REQ
Source Request
10..8DMA_REQ_WE
AT91C_DMA_REQ_WE
Request Write Enable

DMA: AT91_REG DMA_REQDSTREG Destination Software Transaction Request Register

OffsetNameDescription
2..0DMA_DST_REQ
AT91C_DMA_DST_REQ
Destination Request
10..8DMA_REQ_WE
AT91C_DMA_REQ_WE
Request Write Enable

DMA: AT91_REG DMA_SGLREQSRCREG Single Source Software Transaction Request Register

OffsetNameDescription
2..0DMA_S_SG_REQ
AT91C_DMA_S_SG_REQ
Source Single Request
10..8DMA_REQ_WE
AT91C_DMA_REQ_WE
Request Write Enable

DMA: AT91_REG DMA_SGLREQDSTREG Single Destination Software Transaction Request Register

OffsetNameDescription
2..0DMA_D_SG_REQ
AT91C_DMA_D_SG_REQ
Destination Single Request
10..8DMA_REQ_WE
AT91C_DMA_REQ_WE
Request Write Enable

DMA: AT91_REG DMA_LSTREQSRCREG Last Source Software Transaction Request Register

OffsetNameDescription
2..0DMA_LSTSRC
AT91C_DMA_LSTSRC
Source Last Transaction Request
10..8DMA_LSTSR_WE
AT91C_DMA_LSTSR_WE
Source Last Transaction Request Write Enable

DMA: AT91_REG DMA_LSTREQDSTREG Last Destination Software Transaction Request Register

OffsetNameDescription
2..0DMA_LSTDST
AT91C_DMA_LSTDST
Destination Last Transaction Request
10..8DMA_LSTDS_WE
AT91C_DMA_LSTDS_WE
Destination Last Transaction Request Write Enable

DMA: AT91_REG DMA_DMACFGREG DW_ahb_dmac Configuration Register

OffsetNameDescription
2..0DMA_DMA_EN
AT91C_DMA_DMA_EN
Controller Enable

DMA: AT91_REG DMA_CHENREG DW_ahb_dmac Channel Enable Register

OffsetNameDescription
2..0DMA_CH_EN
AT91C_DMA_CH_EN
Channel Enable
10..8DMA_CH_EN_WE
AT91C_DMA_CH_EN_WE
Channel Enable Write Enable

DMA: AT91_REG DMA_DMAIDREG DW_ahb_dmac ID Register

DMA: AT91_REG DMA_DMATESTREG DW_ahb_dmac Test Register

OffsetNameDescription
0DMA_TEST_SLV_IF
AT91C_DMA_TEST_SLV_IF
Test Mode for Slave Interface

DMA: AT91_REG DMA_VERSIONID DW_ahb_dmac Version ID Register