Static Memory Controller Interface Peripheral

SMC (AT91S_SMC) 0xFFFFEC00 (AT91C_BASE_SMC)
SignalSymbolPIO controllerDescription
NCS2(AT91C_PC11_NCS2 )PIOC Periph: A Bit: 11Chip Select Line 2
NCS4_CFCS0(AT91C_PC8_NCS4_CFCS0)PIOC Periph: A Bit: 8Chip Select Line 4
NCS3_NANDCS(AT91C_PC14_NCS3_NANDCS)PIOC Periph: A Bit: 14Chip Select Line 3
NCS6(AT91C_PC13_NCS6 )PIOC Periph: B Bit: 13Chip Select Line 6
CFCE1(AT91C_PC6_CFCE1 )PIOC Periph: B Bit: 6Compact Flash Enable 1
NCS7(AT91C_PC12_NCS7 )PIOC Periph: B Bit: 12Chip Select Line 7
CFCE2(AT91C_PC7_CFCE2 )PIOC Periph: B Bit: 7Compact Flash Enable 2
NCS5_CFCS1(AT91C_PC9_NCS5_CFCS1)PIOC Periph: A Bit: 9Chip Select Line 5

FunctionDescription
AT91F_SMC_CfgPIOConfigure PIO controllers to drive SMC signals


SMC Software API (AT91S_SMC)

OffsetFieldDescription
0x0SMC_SETUP0 (SMC_SETUP) Setup Register for CS 0
0x4SMC_PULSE0 (SMC_PULSE) Pulse Register for CS 0
0x8SMC_CYCLE0 (SMC_CYC) Cycle Register for CS 0
0xCSMC_CTRL0 (SMC_CTRL) Control Register for CS 0
0x10SMC_SETUP1 (SMC_SETUP) Setup Register for CS 1
0x14SMC_PULSE1 (SMC_PULSE) Pulse Register for CS 1
0x18SMC_CYCLE1 (SMC_CYC) Cycle Register for CS 1
0x1CSMC_CTRL1 (SMC_CTRL) Control Register for CS 1
0x20SMC_SETUP2 (SMC_SETUP) Setup Register for CS 2
0x24SMC_PULSE2 (SMC_PULSE) Pulse Register for CS 2
0x28SMC_CYCLE2 (SMC_CYC) Cycle Register for CS 2
0x2CSMC_CTRL2 (SMC_CTRL) Control Register for CS 2
0x30SMC_SETUP3 (SMC_SETUP) Setup Register for CS 3
0x34SMC_PULSE3 (SMC_PULSE) Pulse Register for CS 3
0x38SMC_CYCLE3 (SMC_CYC) Cycle Register for CS 3
0x3CSMC_CTRL3 (SMC_CTRL) Control Register for CS 3
0x40SMC_SETUP4 (SMC_SETUP) Setup Register for CS 4
0x44SMC_PULSE4 (SMC_PULSE) Pulse Register for CS 4
0x48SMC_CYCLE4 (SMC_CYC) Cycle Register for CS 4
0x4CSMC_CTRL4 (SMC_CTRL) Control Register for CS 4
0x50SMC_SETUP5 (SMC_SETUP) Setup Register for CS 5
0x54SMC_PULSE5 (SMC_PULSE) Pulse Register for CS 5
0x58SMC_CYCLE5 (SMC_CYC) Cycle Register for CS 5
0x5CSMC_CTRL5 (SMC_CTRL) Control Register for CS 5
0x60SMC_SETUP6 (SMC_SETUP) Setup Register for CS 6
0x64SMC_PULSE6 (SMC_PULSE) Pulse Register for CS 6
0x68SMC_CYCLE6 (SMC_CYC) Cycle Register for CS 6
0x6CSMC_CTRL6 (SMC_CTRL) Control Register for CS 6
0x70SMC_SETUP7 (SMC_SETUP) Setup Register for CS 7
0x74SMC_PULSE7 (SMC_PULSE) Pulse Register for CS 7
0x78SMC_CYCLE7 (SMC_CYC) Cycle Register for CS 7
0x7CSMC_CTRL7 (SMC_CTRL) Control Register for CS 7

SMC Register Description

SMC: AT91_REG SETUP0 Setup Register for CS 0

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE0 Pulse Register for CS 0

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE0 Cycle Register for CS 0

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL0 Control Register for CS 0

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.

SMC: AT91_REG SETUP1 Setup Register for CS 1

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE1 Pulse Register for CS 1

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE1 Cycle Register for CS 1

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL1 Control Register for CS 1

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.

SMC: AT91_REG SETUP2 Setup Register for CS 2

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE2 Pulse Register for CS 2

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE2 Cycle Register for CS 2

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL2 Control Register for CS 2

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.

SMC: AT91_REG SETUP3 Setup Register for CS 3

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE3 Pulse Register for CS 3

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE3 Cycle Register for CS 3

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL3 Control Register for CS 3

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.

SMC: AT91_REG SETUP4 Setup Register for CS 4

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE4 Pulse Register for CS 4

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE4 Cycle Register for CS 4

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL4 Control Register for CS 4

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.

SMC: AT91_REG SETUP5 Setup Register for CS 5

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE5 Pulse Register for CS 5

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE5 Cycle Register for CS 5

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL5 Control Register for CS 5

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.

SMC: AT91_REG SETUP6 Setup Register for CS 6

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE6 Pulse Register for CS 6

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE6 Cycle Register for CS 6

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL6 Control Register for CS 6

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.

SMC: AT91_REG SETUP7 Setup Register for CS 7

OffsetNameDescription
5..0SMC_NWESETUP
AT91C_SMC_NWESETUP
NWE Setup Length
NWE Setup Length = 128*SMC_NWESETUP[5] + SMC_NWESETUP[4:0]
13..8SMC_NCSSETUPWR
AT91C_SMC_NCSSETUPWR
NCS Setup Length in WRite Access
NCS Setup Length = 128*SMC_NCSSETUPWR[5] + SMC_NCSSETUPWR[4:0]
21..16SMC_NRDSETUP
AT91C_SMC_NRDSETUP
NRD Setup Length
NRD Setup Length = 128*SMC_NRDSETUP[5] + SMC_NRDSETUP[4:0]
29..24SMC_NCSSETUPRD
AT91C_SMC_NCSSETUPRD
NCS Setup Length in ReaD Access
NCS Setup Length = 128*SMC_NCSSETUPRD[5] + SMC_NCSSETUPRD[4:0]

SMC: AT91_REG PULSE7 Pulse Register for CS 7

OffsetNameDescription
6..0SMC_NWEPULSE
AT91C_SMC_NWEPULSE
NWE Pulse Length
NWE Pulse Length = 256*SMC_NWEPULSE[6] + SMC_NWEPULSE[5:0]
14..8SMC_NCSPULSEWR
AT91C_SMC_NCSPULSEWR
NCS Pulse Length in WRite Access
NCS Pulse Length = 256*SMC_NCSPULSEWR[6] + SMC_NCSPULSEWR[5:0]
22..16SMC_NRDPULSE
AT91C_SMC_NRDPULSE
NRD Pulse Length
NRD Pulse Length = 256*SMC_NRDPULSE[6] + SMC_NRDPULSE[5:0]
30..24SMC_NCSPULSERD
AT91C_SMC_NCSPULSERD
NCS Pulse Length in ReaD Access
NCS Pulse Length = 256*SMC_NCSPULSERD[6] + SMC_NCSPULSERD[5:0]

SMC: AT91_REG CYCLE7 Cycle Register for CS 7

OffsetNameDescription
8..0SMC_NWECYCLE
AT91C_SMC_NWECYCLE
Total Write Cycle Length
Total Write Cycle Length = 256*SMC_NWECYCLE[8:7] + SMC_NWECYCLE[6:0]
24..16SMC_NRDCYCLE
AT91C_SMC_NRDCYCLE
Total Read Cycle Length
Total Read Cycle Length = 256*SMC_NRDCYCLE[8:7] + SMC_NRDCYCLE[6:0]

SMC: AT91_REG CTRL7 Control Register for CS 7

OffsetNameDescription
0SMC_READMODE
AT91C_SMC_READMODE
Read Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NRD signal.
1SMC_WRITEMODE
AT91C_SMC_WRITEMODE
Write Mode
0: Read operation controled by NCS signal.
1: Read operation controled by NWE signal.
6..5SMC_NWAITM
AT91C_SMC_NWAITM
NWAIT Mode
0: External NWAIT disabled
1: Reserved.
2: External NWAIT enabled in frozen mode.
3: External NWAIT enabled in ready mode.
ValueLabelDescription
0SMC_NWAITM_NWAIT_DISABLE
AT91C_SMC_NWAITM_NWAIT_DISABLE

External NWAIT disabled.
2SMC_NWAITM_NWAIT_ENABLE_FROZEN
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN

External NWAIT enabled in frozen mode.
3SMC_NWAITM_NWAIT_ENABLE_READY
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY

External NWAIT enabled in ready mode.
8SMC_BAT
AT91C_SMC_BAT
Byte Access Type
0: Byte Select.
1: Byte Write.
ValueLabelDescription
0SMC_BAT_BYTE_SELECT
AT91C_SMC_BAT_BYTE_SELECT

Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
1SMC_BAT_BYTE_WRITE
AT91C_SMC_BAT_BYTE_WRITE

Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
13..12SMC_DBW
AT91C_SMC_DBW
Data Bus Width
0: 8 bits.
1: 16 bits.
3: 32 bits.
4: Reserved
ValueLabelDescription
0SMC_DBW_WIDTH_EIGTH_BITS
AT91C_SMC_DBW_WIDTH_EIGTH_BITS

8 bits.
1SMC_DBW_WIDTH_SIXTEEN_BITS
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS

16 bits.
2SMC_DBW_WIDTH_THIRTY_TWO_BITS
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS

32 bits.
19..16SMC_TDF
AT91C_SMC_TDF
Data Float Time.
0 up to 15 cycles.
20SMC_TDFEN
AT91C_SMC_TDFEN
TDF Enabled.
0: TDF optimisation is disabled.
1: TDF optimisation is enabled.
24SMC_PMEN
AT91C_SMC_PMEN
Page Mode Enabled.
0: Page Mode is disabled.
1: Page Mode is enabled.
29..28SMC_PS
AT91C_SMC_PS
Page Size
0: 4 bytes.
1: 8 bytes.
2: 16 bytes.
3: 32 bytes.
ValueLabelDescription
0SMC_PS_SIZE_FOUR_BYTES
AT91C_SMC_PS_SIZE_FOUR_BYTES

4 bytes.
1SMC_PS_SIZE_EIGHT_BYTES
AT91C_SMC_PS_SIZE_EIGHT_BYTES

8 bytes.
2SMC_PS_SIZE_SIXTEEN_BYTES
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES

16 bytes.
3SMC_PS_SIZE_THIRTY_TWO_BYTES
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES

32 bytes.