LCD Controller Peripheral

LCDC (AT91S_LCDC) 0x00600000 (AT91C_BASE_LCDC)
Periph ID AICSymbolDescription
21 (AT91C_ID_LCDC)LCD Controller

SignalSymbolPIO controllerDescription
LCDVSYNC(AT91C_PB0_LCDVSYNC)PIOB Periph: A Bit: 0LCD Vertical Synchronization
LCDCC(AT91C_PB4_LCDCC )PIOB Periph: A Bit: 4LCD Contrast Control
LCDD10(AT91C_PB15_LCDD10 )PIOB Periph: A Bit: 15LCD Data Bus Bit 10
LCDD11(AT91C_PB16_LCDD11 )PIOB Periph: A Bit: 16LCD Data Bus Bit 11
LCDD12(AT91C_PB17_LCDD12 )PIOB Periph: A Bit: 17LCD Data Bus Bit 12
LCDD20(AT91C_PB25_LCDD20 )PIOB Periph: B Bit: 25LCD Data Bus Bit 20
LCDD13(AT91C_PB18_LCDD13 )PIOB Periph: A Bit: 18LCD Data Bus Bit 13
LCDD21(AT91C_PB26_LCDD21 )PIOB Periph: B Bit: 26LCD Data Bus Bit 21
LCDD14(AT91C_PB19_LCDD14 )PIOB Periph: A Bit: 19LCD Data Bus Bit 14
LCDD22(AT91C_PB27_LCDD22 )PIOB Periph: B Bit: 27LCD Data Bus Bit 22
LCDD15(AT91C_PB20_LCDD15 )PIOB Periph: A Bit: 20LCD Data Bus Bit 15
LCDD23(AT91C_PB28_LCDD23 )PIOB Periph: B Bit: 28LCD Data Bus Bit 23
LCDD0(AT91C_PB5_LCDD0 )PIOB Periph: A Bit: 5LCD Data Bus Bit 0
LCDD16(AT91C_PB21_LCDD16 )PIOB Periph: B Bit: 21LCD Data Bus Bit 16
LCDD1(AT91C_PB6_LCDD1 )PIOB Periph: A Bit: 6LCD Data Bus Bit 1
LCDD17(AT91C_PB22_LCDD17 )PIOB Periph: B Bit: 22LCD Data Bus Bit 17
LCDD2(AT91C_PB4_LCDD2 )PIOB Periph: B Bit: 4LCD Data Bus Bit 2
LCDD2(AT91C_PB7_LCDD2 )PIOB Periph: A Bit: 7LCD Data Bus Bit 2
LCDDEN(AT91C_PB3_LCDDEN )PIOB Periph: A Bit: 3LCD Data Enable
LCDD3(AT91C_PB8_LCDD3 )PIOB Periph: A Bit: 8LCD Data Bus Bit 3
LCDD18(AT91C_PB23_LCDD18 )PIOB Periph: B Bit: 23LCD Data Bus Bit 18
LCDD4(AT91C_PB9_LCDD4 )PIOB Periph: A Bit: 9LCD Data Bus Bit 4
LCDD19(AT91C_PB24_LCDD19 )PIOB Periph: B Bit: 24LCD Data Bus Bit 19
LCDD5(AT91C_PB10_LCDD5 )PIOB Periph: A Bit: 10LCD Data Bus Bit 5
LCDD6(AT91C_PB11_LCDD6 )PIOB Periph: A Bit: 11LCD Data Bus Bit 6
LCDDOTCK(AT91C_PB2_LCDDOTCK)PIOB Periph: A Bit: 2LCD Dot Clock
LCDD7(AT91C_PB12_LCDD7 )PIOB Periph: A Bit: 12LCD Data Bus Bit 7
LCDHSYNC(AT91C_PB1_LCDHSYNC)PIOB Periph: A Bit: 1LCD Horizontal Synchronization
LCDD8(AT91C_PB13_LCDD8 )PIOB Periph: A Bit: 13LCD Data Bus Bit 8
LCDD9(AT91C_PB14_LCDD9 )PIOB Periph: A Bit: 14LCD Data Bus Bit 9

FunctionDescription
AT91F_LCDC_CfgPMCEnable Peripheral clock in PMC for LCDC
AT91F_LCDC_CfgPIOConfigure PIO controllers to drive LCDC signals


LCDC_16B_TFT (AT91S_LCDC) 0x00600000 (AT91C_BASE_LCDC_16B_TFT)
SignalSymbolPIO controllerDescription
LCDD10(AT91C_PB10_LCDD10 )PIOB Periph: B Bit: 10LCD Data Bus Bit 10
LCDD11(AT91C_PB11_LCDD11 )PIOB Periph: B Bit: 11LCD Data Bus Bit 11
LCDD20(AT91C_PB17_LCDD20 )PIOB Periph: B Bit: 17LCD Data Bus Bit 20
LCDD12(AT91C_PB12_LCDD12 )PIOB Periph: B Bit: 12LCD Data Bus Bit 12
LCDD21(AT91C_PB18_LCDD21 )PIOB Periph: B Bit: 18LCD Data Bus Bit 21
LCDD13(AT91C_PB13_LCDD13 )PIOB Periph: B Bit: 13LCD Data Bus Bit 13
LCDD22(AT91C_PB19_LCDD22 )PIOB Periph: B Bit: 19LCD Data Bus Bit 22
LCDD14(AT91C_PB14_LCDD14 )PIOB Periph: B Bit: 14LCD Data Bus Bit 14
LCDD23(AT91C_PB20_LCDD23 )PIOB Periph: B Bit: 20LCD Data Bus Bit 23
LCDD15(AT91C_PB15_LCDD15 )PIOB Periph: B Bit: 15LCD Data Bus Bit 15
LCDD3(AT91C_PB5_LCDD3 )PIOB Periph: B Bit: 5LCD Data Bus Bit 3
LCDD19(AT91C_PB16_LCDD19 )PIOB Periph: B Bit: 16LCD Data Bus Bit 19
LCDD4(AT91C_PB6_LCDD4 )PIOB Periph: B Bit: 6LCD Data Bus Bit 4
LCDD5(AT91C_PB7_LCDD5 )PIOB Periph: B Bit: 7LCD Data Bus Bit 5
LCDD6(AT91C_PB8_LCDD6 )PIOB Periph: B Bit: 8LCD Data Bus Bit 6
LCDD7(AT91C_PB9_LCDD7 )PIOB Periph: B Bit: 9LCD Data Bus Bit 7

FunctionDescription
AT91F_LCDC_16B_TFT_CfgPIOConfigure PIO controllers to drive LCDC_16B_TFT signals


LCDC Software API (AT91S_LCDC)

OffsetFieldDescription
0x0LCDC_BA1 (LCDC_BA)DMA Base Address Register 1
0x4LCDC_BA2 (LCDC_BA)DMA Base Address Register 2
0x8LCDC_FRMP1DMA Frame Pointer Register 1
0xCLCDC_FRMP2DMA Frame Pointer Register 2
0x10LCDC_FRMA1 (LCDC_FRMA)DMA Frame Address Register 1
0x14LCDC_FRMA2 (LCDC_FRMA)DMA Frame Address Register 2
0x18LCDC_FRMCFGDMA Frame Configuration Register
0x1CLCDC_DMACONDMA Control Register
0x20LCDC_DMA2DCFGDMA 2D addressing configuration
0x800LCDC_LCDCON1LCD Control 1 Register
0x804LCDC_LCDCON2LCD Control 2 Register
0x808LCDC_TIM1LCD Timing Config 1 Register
0x80CLCDC_TIM2LCD Timing Config 2 Register
0x810LCDC_LCDFRCFGLCD Frame Config Register
0x814LCDC_FIFOLCD FIFO Register
0x818LCDC_MVALLCD Mode Toggle Rate Value Register
0x81CLCDC_DP1_2Dithering Pattern DP1_2 Register
0x820LCDC_DP4_7Dithering Pattern DP4_7 Register
0x824LCDC_DP3_5Dithering Pattern DP3_5 Register
0x828LCDC_DP2_3Dithering Pattern DP2_3 Register
0x82CLCDC_DP5_7Dithering Pattern DP5_7 Register
0x830LCDC_DP3_4Dithering Pattern DP3_4 Register
0x834LCDC_DP4_5Dithering Pattern DP4_5 Register
0x838LCDC_DP6_7Dithering Pattern DP6_7 Register
0x83CLCDC_PWRCONPower Control Register
0x840LCDC_CTRSTCONContrast Control Register
0x844LCDC_CTRSTVALContrast Value Register
0x848LCDC_IERInterrupt Enable Register
0x84CLCDC_IDRInterrupt Disable Register
0x850LCDC_IMRInterrupt Mask Register
0x854LCDC_ISRInterrupt Enable Register
0x858LCDC_ICRInterrupt Clear Register
0x85CLCDC_GPRGeneral Purpose Register
0x860LCDC_ITRInterrupts Test Register
0x864LCDC_IRRInterrupts Raw Status Register
0xC00LCDC_LUT_ENTRY[256] (LCDC_LUT_ENTRY)LUT Entries Register

FunctionDescription
AT91F_LCDC_CORE_CfgPMCEnable LCD Controller Clock
AT91F_LCDC_DMA_CfgPMCEnable DMA Clock

LCDC Register Description

LCDC: AT91_REG LCDC_BA1 DMA Base Address Register 1

LCDC: AT91_REG LCDC_BA2 DMA Base Address Register 2

LCDC: AT91_REG LCDC_FRMP1 DMA Frame Pointer Register 1

OffsetNameDescription
21..0LCDC_FRMPT1
AT91C_LCDC_FRMPT1
Frame Pointer Address 1

LCDC: AT91_REG LCDC_FRMP2 DMA Frame Pointer Register 2

OffsetNameDescription
20..0LCDC_FRMPT2
AT91C_LCDC_FRMPT2
Frame Pointer Address 2

LCDC: AT91_REG LCDC_FRMA1 DMA Frame Address Register 1

LCDC: AT91_REG LCDC_FRMA2 DMA Frame Address Register 2

LCDC: AT91_REG LCDC_FRMCFG DMA Frame Configuration Register

OffsetNameDescription
21..0LCDC_FRSIZE
AT91C_LCDC_FRSIZE
FRAME SIZE
27..24LCDC_BLENGTH
AT91C_LCDC_BLENGTH
BURST LENGTH

LCDC: AT91_REG LCDC_DMACON DMA Control Register

OffsetNameDescription
0LCDC_DMAEN
AT91C_LCDC_DMAEN
DAM Enable
1: DMA is enable.
0: DMA is disable
1LCDC_DMARST
AT91C_LCDC_DMARST
DMA Reset (WO)
1: DMA is Reset.
2LCDC_DMABUSY
AT91C_LCDC_DMABUSY
DMA Reset (WO)
1: DMA is Busy.
0: DMA is Idle

LCDC: AT91_REG LCDC_DMA2DCFG DMA 2D addressing configuration

OffsetNameDescription
15..0LCDC_ADDRINC
AT91C_LCDC_ADDRINC
Number of 32b words that the DMA must jump when going to the next line
28..24LCDC_PIXELOFF
AT91C_LCDC_PIXELOFF
Offset (in bits) of the first pixel of the screen in the memory word which contain it

LCDC: AT91_REG LCDC_LCDCON1 LCD Control 1 Register

OffsetNameDescription
0LCDC_BYPASS
AT91C_LCDC_BYPASS
Bypass lcd_pccklk divider
1: lcd_pccklk divider is bypassed.
0: lcd_pccklk divider is enable
20..12LCDC_CLKVAL
AT91C_LCDC_CLKVAL
9-bit Divider for pixel clock frequency
lcd_pccklk = system_clk/(2*CLKVAL)
31..21LCDC_LINCNT
AT91C_LCDC_LINCNT
Line Counter (RO)
Down count from LINEVAL to 0

LCDC: AT91_REG LCDC_LCDCON2 LCD Control 2 Register

OffsetNameDescription
1..0LCDC_DISTYPE
AT91C_LCDC_DISTYPE
Display Type
STN Mono, STN Color, TFT
ValueLabelDescription
0LCDC_DISTYPE_STNMONO
AT91C_LCDC_DISTYPE_STNMONO

STN Mono
1LCDC_DISTYPE_STNCOLOR
AT91C_LCDC_DISTYPE_STNCOLOR

STN Color
2LCDC_DISTYPE_TFT
AT91C_LCDC_DISTYPE_TFT

TFT
2LCDC_SCANMOD
AT91C_LCDC_SCANMOD
Scan Mode
Single Scan or Dual Scan
ValueLabelDescription
0LCDC_SCANMOD_SINGLESCAN
AT91C_LCDC_SCANMOD_SINGLESCAN

Single Scan
1LCDC_SCANMOD_DUALSCAN
AT91C_LCDC_SCANMOD_DUALSCAN

Dual Scan
4..3LCDC_IFWIDTH
AT91C_LCDC_IFWIDTH
Interface Width
4, 8 or 16 Bits
ValueLabelDescription
0LCDC_IFWIDTH_FOURBITSWIDTH
AT91C_LCDC_IFWIDTH_FOURBITSWIDTH

4 Bits
1LCDC_IFWIDTH_EIGTHBITSWIDTH
AT91C_LCDC_IFWIDTH_EIGTHBITSWIDTH

8 Bits
2LCDC_IFWIDTH_SIXTEENBITSWIDTH
AT91C_LCDC_IFWIDTH_SIXTEENBITSWIDTH

16 Bits
7..5LCDC_PIXELSIZE
AT91C_LCDC_PIXELSIZE
Bits per pixel
1, 2, 4, 8, 16 or 24 Bits
ValueLabelDescription
0LCDC_PIXELSIZE_ONEBITSPERPIXEL
AT91C_LCDC_PIXELSIZE_ONEBITSPERPIXEL

1 Bits
1LCDC_PIXELSIZE_TWOBITSPERPIXEL
AT91C_LCDC_PIXELSIZE_TWOBITSPERPIXEL

2 Bits
2LCDC_PIXELSIZE_FOURBITSPERPIXEL
AT91C_LCDC_PIXELSIZE_FOURBITSPERPIXEL

4 Bits
3LCDC_PIXELSIZE_EIGTHBITSPERPIXEL
AT91C_LCDC_PIXELSIZE_EIGTHBITSPERPIXEL

8 Bits
4LCDC_PIXELSIZE_SIXTEENBITSPERPIXEL
AT91C_LCDC_PIXELSIZE_SIXTEENBITSPERPIXEL

16 Bits
5LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL
AT91C_LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL

24 Bits
8LCDC_INVVD
AT91C_LCDC_INVVD
lcd datas polarity
Normal or Inverted
ValueLabelDescription
0LCDC_INVVD_NORMALPOL
AT91C_LCDC_INVVD_NORMALPOL

Normal Polarity
1LCDC_INVVD_INVERTEDPOL
AT91C_LCDC_INVVD_INVERTEDPOL

Inverted Polarity
9LCDC_INVFRAME
AT91C_LCDC_INVFRAME
lcd vsync polarity
Normal or Inverted
ValueLabelDescription
0LCDC_INVFRAME_NORMALPOL
AT91C_LCDC_INVFRAME_NORMALPOL

Normal Polarity
1LCDC_INVFRAME_INVERTEDPOL
AT91C_LCDC_INVFRAME_INVERTEDPOL

Inverted Polarity
10LCDC_INVLINE
AT91C_LCDC_INVLINE
lcd hsync polarity
Normal or Inverted
ValueLabelDescription
0LCDC_INVLINE_NORMALPOL
AT91C_LCDC_INVLINE_NORMALPOL

Normal Polarity
1LCDC_INVLINE_INVERTEDPOL
AT91C_LCDC_INVLINE_INVERTEDPOL

Inverted Polarity
11LCDC_INVCLK
AT91C_LCDC_INVCLK
lcd pclk polarity
Normal or Inverted
ValueLabelDescription
0LCDC_INVCLK_NORMALPOL
AT91C_LCDC_INVCLK_NORMALPOL

Normal Polarity
1LCDC_INVCLK_INVERTEDPOL
AT91C_LCDC_INVCLK_INVERTEDPOL

Inverted Polarity
12LCDC_INVDVAL
AT91C_LCDC_INVDVAL
lcd dval polarity
Normal or Inverted
ValueLabelDescription
0LCDC_INVDVAL_NORMALPOL
AT91C_LCDC_INVDVAL_NORMALPOL

Normal Polarity
1LCDC_INVDVAL_INVERTEDPOL
AT91C_LCDC_INVDVAL_INVERTEDPOL

Inverted Polarity
15LCDC_CLKMOD
AT91C_LCDC_CLKMOD
lcd pclk Mode
0: Active during display period.
1: Always active.
ValueLabelDescription
0LCDC_CLKMOD_ACTIVEONLYDISP
AT91C_LCDC_CLKMOD_ACTIVEONLYDISP

Active during display period
1LCDC_CLKMOD_ALWAYSACTIVE
AT91C_LCDC_CLKMOD_ALWAYSACTIVE

Always Active
31LCDC_MEMOR
AT91C_LCDC_MEMOR
lcd pclk Mode
0: Big Endian.
1: Little Endian.
ValueLabelDescription
0LCDC_MEMOR_BIGIND
AT91C_LCDC_MEMOR_BIGIND

Big Endian
1LCDC_MEMOR_LITTLEIND
AT91C_LCDC_MEMOR_LITTLEIND

Little Endian

LCDC: AT91_REG LCDC_TIM1 LCD Timing Config 1 Register

OffsetNameDescription
7..0LCDC_VFP
AT91C_LCDC_VFP
Vertical Front Porch
15..8LCDC_VBP
AT91C_LCDC_VBP
Vertical Back Porch
21..16LCDC_VPW
AT91C_LCDC_VPW
Vertical Synchronization Pulse Width
27..24LCDC_VHDLY
AT91C_LCDC_VHDLY
Vertical to Horizontal Delay

LCDC: AT91_REG LCDC_TIM2 LCD Timing Config 2 Register

OffsetNameDescription
7..0LCDC_HBP
AT91C_LCDC_HBP
Horizontal Back Porch
13..8LCDC_HPW
AT91C_LCDC_HPW
Horizontal Synchronization Pulse Width
31..22LCDC_HFP
AT91C_LCDC_HFP
Horizontal Front Porch

LCDC: AT91_REG LCDC_LCDFRCFG LCD Frame Config Register

OffsetNameDescription
10..0LCDC_LINEVAL
AT91C_LCDC_LINEVAL
Vertical Size of LCD Module
31..21LCDC_HOZVAL
AT91C_LCDC_HOZVAL
Horizontal Size of LCD Module

LCDC: AT91_REG LCDC_FIFO LCD FIFO Register

OffsetNameDescription
15..0LCDC_FIFOTH
AT91C_LCDC_FIFOTH
FIFO Threshold

LCDC: AT91_REG LCDC_MVAL LCD Mode Toggle Rate Value Register

OffsetNameDescription
7..0LCDC_MVALUE
AT91C_LCDC_MVALUE
Toggle Rate Value
31LCDC_MMODE
AT91C_LCDC_MMODE
Toggle Rate Sel
0: Each Frame.
1: Defined by MVAL
ValueLabelDescription
0LCDC_MMODE_EACHFRAME
AT91C_LCDC_MMODE_EACHFRAME

Each Frame
1LCDC_MMODE_MVALDEFINED
AT91C_LCDC_MMODE_MVALDEFINED

Defined by MVAL

LCDC: AT91_REG LCDC_DP1_2 Dithering Pattern DP1_2 Register

OffsetNameDescription
7..0LCDC_DP1_2_FIELD
AT91C_LCDC_DP1_2_FIELD
Ratio

LCDC: AT91_REG LCDC_DP4_7 Dithering Pattern DP4_7 Register

OffsetNameDescription
27..0LCDC_DP4_7_FIELD
AT91C_LCDC_DP4_7_FIELD
Ratio

LCDC: AT91_REG LCDC_DP3_5 Dithering Pattern DP3_5 Register

OffsetNameDescription
19..0LCDC_DP3_5_FIELD
AT91C_LCDC_DP3_5_FIELD
Ratio

LCDC: AT91_REG LCDC_DP2_3 Dithering Pattern DP2_3 Register

OffsetNameDescription
11..0LCDC_DP2_3_FIELD
AT91C_LCDC_DP2_3_FIELD
Ratio

LCDC: AT91_REG LCDC_DP5_7 Dithering Pattern DP5_7 Register

OffsetNameDescription
27..0LCDC_DP5_7_FIELD
AT91C_LCDC_DP5_7_FIELD
Ratio

LCDC: AT91_REG LCDC_DP3_4 Dithering Pattern DP3_4 Register

OffsetNameDescription
15..0LCDC_DP3_4_FIELD
AT91C_LCDC_DP3_4_FIELD
Ratio

LCDC: AT91_REG LCDC_DP4_5 Dithering Pattern DP4_5 Register

OffsetNameDescription
19..0LCDC_DP4_5_FIELD
AT91C_LCDC_DP4_5_FIELD
Ratio

LCDC: AT91_REG LCDC_DP6_7 Dithering Pattern DP6_7 Register

OffsetNameDescription
27..0LCDC_DP6_7_FIELD
AT91C_LCDC_DP6_7_FIELD
Ratio

LCDC: AT91_REG LCDC_PWRCON Power Control Register

OffsetNameDescription
0LCDC_PWR
AT91C_LCDC_PWR
LCD Module Power Control
7..1LCDC_GUARDT
AT91C_LCDC_GUARDT
Delay in Frame Period
31LCDC_BUSY
AT91C_LCDC_BUSY
Read Only : 1 indicates that LCDC is busy
ValueLabelDescription
0LCDC_BUSY_LCDNOTBUSY
AT91C_LCDC_BUSY_LCDNOTBUSY

LCD is Not Busy
1LCDC_BUSY_LCDBUSY
AT91C_LCDC_BUSY_LCDBUSY

LCD is Busy

LCDC: AT91_REG LCDC_CTRSTCON Contrast Control Register

OffsetNameDescription
1..0LCDC_PS
AT91C_LCDC_PS
LCD Contrast Counter Prescaler
ValueLabelDescription
0LCDC_PS_NOTDIVIDED
AT91C_LCDC_PS_NOTDIVIDED

Counter Freq is System Freq.
1LCDC_PS_DIVIDEDBYTWO
AT91C_LCDC_PS_DIVIDEDBYTWO

Counter Freq is System Freq divided by 2.
2LCDC_PS_DIVIDEDBYFOUR
AT91C_LCDC_PS_DIVIDEDBYFOUR

Counter Freq is System Freq divided by 4.
3LCDC_PS_DIVIDEDBYEIGHT
AT91C_LCDC_PS_DIVIDEDBYEIGHT

Counter Freq is System Freq divided by 8.
2LCDC_POL
AT91C_LCDC_POL
Polarity of output Pulse
ValueLabelDescription
0LCDC_POL_NEGATIVEPULSE
AT91C_LCDC_POL_NEGATIVEPULSE

Negative Pulse
1LCDC_POL_POSITIVEPULSE
AT91C_LCDC_POL_POSITIVEPULSE

Positive Pulse
3LCDC_ENA
AT91C_LCDC_ENA
PWM generator Control
ValueLabelDescription
0LCDC_ENA_PWMGEMDISABLED
AT91C_LCDC_ENA_PWMGEMDISABLED

PWM Generator Disabled
1LCDC_ENA_PWMGEMENABLED
AT91C_LCDC_ENA_PWMGEMENABLED

PWM Generator Disabled

LCDC: AT91_REG LCDC_CTRSTVAL Contrast Value Register

OffsetNameDescription
7..0LCDC_CVAL
AT91C_LCDC_CVAL
PWM Compare Value

LCDC: AT91_REG LCDC_IER Interrupt Enable Register


0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
OffsetNameDescription
0LCDC_LNI
AT91C_LCDC_LNI
Line Interrupt
1LCDC_LSTLNI
AT91C_LCDC_LSTLNI
Last Line Interrupt
2LCDC_EOFI
AT91C_LCDC_EOFI
End Of Frame Interrupt
4LCDC_UFLWI
AT91C_LCDC_UFLWI
FIFO Underflow Interrupt
5LCDC_OWRI
AT91C_LCDC_OWRI
Over Write Interrupt
6LCDC_MERI
AT91C_LCDC_MERI
Memory Error Interrupt

LCDC: AT91_REG LCDC_IDR Interrupt Disable Register


0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
OffsetNameDescription
0LCDC_LNI
AT91C_LCDC_LNI
Line Interrupt
1LCDC_LSTLNI
AT91C_LCDC_LSTLNI
Last Line Interrupt
2LCDC_EOFI
AT91C_LCDC_EOFI
End Of Frame Interrupt
4LCDC_UFLWI
AT91C_LCDC_UFLWI
FIFO Underflow Interrupt
5LCDC_OWRI
AT91C_LCDC_OWRI
Over Write Interrupt
6LCDC_MERI
AT91C_LCDC_MERI
Memory Error Interrupt

LCDC: AT91_REG LCDC_IMR Interrupt Mask Register


0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
OffsetNameDescription
0LCDC_LNI
AT91C_LCDC_LNI
Line Interrupt
1LCDC_LSTLNI
AT91C_LCDC_LSTLNI
Last Line Interrupt
2LCDC_EOFI
AT91C_LCDC_EOFI
End Of Frame Interrupt
4LCDC_UFLWI
AT91C_LCDC_UFLWI
FIFO Underflow Interrupt
5LCDC_OWRI
AT91C_LCDC_OWRI
Over Write Interrupt
6LCDC_MERI
AT91C_LCDC_MERI
Memory Error Interrupt

LCDC: AT91_REG LCDC_ISR Interrupt Enable Register


0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
OffsetNameDescription
0LCDC_LNI
AT91C_LCDC_LNI
Line Interrupt
1LCDC_LSTLNI
AT91C_LCDC_LSTLNI
Last Line Interrupt
2LCDC_EOFI
AT91C_LCDC_EOFI
End Of Frame Interrupt
4LCDC_UFLWI
AT91C_LCDC_UFLWI
FIFO Underflow Interrupt
5LCDC_OWRI
AT91C_LCDC_OWRI
Over Write Interrupt
6LCDC_MERI
AT91C_LCDC_MERI
Memory Error Interrupt

LCDC: AT91_REG LCDC_ICR Interrupt Clear Register


0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
OffsetNameDescription
0LCDC_LNI
AT91C_LCDC_LNI
Line Interrupt
1LCDC_LSTLNI
AT91C_LCDC_LSTLNI
Last Line Interrupt
2LCDC_EOFI
AT91C_LCDC_EOFI
End Of Frame Interrupt
4LCDC_UFLWI
AT91C_LCDC_UFLWI
FIFO Underflow Interrupt
5LCDC_OWRI
AT91C_LCDC_OWRI
Over Write Interrupt
6LCDC_MERI
AT91C_LCDC_MERI
Memory Error Interrupt

LCDC: AT91_REG LCDC_GPR General Purpose Register

OffsetNameDescription
7..0LCDC_GPRBUS
AT91C_LCDC_GPRBUS
8 bits available

LCDC: AT91_REG LCDC_ITR Interrupts Test Register


0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
OffsetNameDescription
0LCDC_LNI
AT91C_LCDC_LNI
Line Interrupt
1LCDC_LSTLNI
AT91C_LCDC_LSTLNI
Last Line Interrupt
2LCDC_EOFI
AT91C_LCDC_EOFI
End Of Frame Interrupt
4LCDC_UFLWI
AT91C_LCDC_UFLWI
FIFO Underflow Interrupt
5LCDC_OWRI
AT91C_LCDC_OWRI
Over Write Interrupt
6LCDC_MERI
AT91C_LCDC_MERI
Memory Error Interrupt

LCDC: AT91_REG LCDC_IRR Interrupts Raw Status Register


0 = Corresponding interrupt condition is false.
1 = Corresponding interrupt condition is true.
OffsetNameDescription
0LCDC_LNI
AT91C_LCDC_LNI
Line Interrupt
1LCDC_LSTLNI
AT91C_LCDC_LSTLNI
Last Line Interrupt
2LCDC_EOFI
AT91C_LCDC_EOFI
End Of Frame Interrupt
4LCDC_UFLWI
AT91C_LCDC_UFLWI
FIFO Underflow Interrupt
5LCDC_OWRI
AT91C_LCDC_OWRI
Over Write Interrupt
6LCDC_MERI
AT91C_LCDC_MERI
Memory Error Interrupt

LCDC: AT91_REG LCDC_LUT_ENTRY LUT Entries Register