AHB Matrix Interface Peripheral

MATRIX (AT91S_MATRIX) 0xFFFFEE00 (AT91C_BASE_MATRIX)

MATRIX Software API (AT91S_MATRIX)

OffsetFieldDescription
0x0MATRIX_MCFG0 Master Configuration Register 0 (ram96k)
0x4MATRIX_MCFG1 Master Configuration Register 1 (rom)
0x8MATRIX_MCFG2 Master Configuration Register 2 (hperiphs)
0xCMATRIX_MCFG3 Master Configuration Register 3 (ebi)
0x10MATRIX_MCFG4 Master Configuration Register 4 (bridge)
0x14MATRIX_MCFG5 Master Configuration Register 5 (mailbox)
0x40MATRIX_SCFG0 Slave Configuration Register 0 (ram96k)
0x44MATRIX_SCFG1 Slave Configuration Register 1 (rom)
0x48MATRIX_SCFG2 Slave Configuration Register 2 (hperiphs)
0x4CMATRIX_SCFG3 Slave Configuration Register 3 (ebi)
0x50MATRIX_SCFG4 Slave Configuration Register 4 (bridge)
0x80MATRIX_PRAS0 PRAS0 (ram0)
0x88MATRIX_PRAS1 PRAS1 (ram1)
0x90MATRIX_PRAS2 PRAS2 (ram2)
0x98MATRIX_PRAS3 PRAS3 (ebi)
0xA0MATRIX_PRAS4 PRAS4 (periph)
0x100MATRIX_MRCR Master Remp Control Register

FunctionDescription
AT91F_MATRIX_Disable_Remap_ARM-DDisable Remap of ARM-D
AT91F_MATRIX_Disable_Remap_ARMDisable Remap of ARM
AT91F_MATRIX_Remap_ARMIEnable Remap of ARM-I
AT91F_MATRIX_Remap_ARMEnable Remap of ARM
AT91F_MATRIX_Disable_Remap_ARMIDisable Remap of ARM-I
AT91F_MATRIX_Remap_ARMDEnable Remap of ARM-D

MATRIX Register Description

MATRIX: AT91_REG MATRIX_MCFG0 Master Configuration Register 0 (ram96k)

MATRIX: AT91_REG MATRIX_MCFG1 Master Configuration Register 1 (rom)

MATRIX: AT91_REG MATRIX_MCFG2 Master Configuration Register 2 (hperiphs)

MATRIX: AT91_REG MATRIX_MCFG3 Master Configuration Register 3 (ebi)

MATRIX: AT91_REG MATRIX_MCFG4 Master Configuration Register 4 (bridge)

MATRIX: AT91_REG MATRIX_MCFG5 Master Configuration Register 5 (mailbox)

MATRIX: AT91_REG MATRIX_SCFG0 Slave Configuration Register 0 (ram96k)

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
20..18MATRIX_FIXED_DEFMSTR0
AT91C_MATRIX_FIXED_DEFMSTR0
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR0_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR0_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR0_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3

HPDC3 Master is Default Master
3MATRIX_FIXED_DEFMSTR0_LCDC
AT91C_MATRIX_FIXED_DEFMSTR0_LCDC

LCDC Master is Default Master
4MATRIX_FIXED_DEFMSTR0_DMA
AT91C_MATRIX_FIXED_DEFMSTR0_DMA

DMA Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG1 Slave Configuration Register 1 (rom)

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
20..18MATRIX_FIXED_DEFMSTR1
AT91C_MATRIX_FIXED_DEFMSTR1
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR1_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR1_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR1_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3

HPDC3 Master is Default Master
3MATRIX_FIXED_DEFMSTR1_LCDC
AT91C_MATRIX_FIXED_DEFMSTR1_LCDC

LCDC Master is Default Master
4MATRIX_FIXED_DEFMSTR1_DMA
AT91C_MATRIX_FIXED_DEFMSTR1_DMA

DMA Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG2 Slave Configuration Register 2 (hperiphs)

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
18MATRIX_FIXED_DEFMSTR2
AT91C_MATRIX_FIXED_DEFMSTR2
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR2_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR2_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D

ARM926EJ-S Data Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG3 Slave Configuration Register 3 (ebi)

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
20..18MATRIX_FIXED_DEFMSTR3
AT91C_MATRIX_FIXED_DEFMSTR3
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR3_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR3_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR3_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3

HPDC3 Master is Default Master
3MATRIX_FIXED_DEFMSTR3_LCDC
AT91C_MATRIX_FIXED_DEFMSTR3_LCDC

LCDC Master is Default Master
4MATRIX_FIXED_DEFMSTR3_DMA
AT91C_MATRIX_FIXED_DEFMSTR3_DMA

DMA Master is Default Master

MATRIX: AT91_REG MATRIX_SCFG4 Slave Configuration Register 4 (bridge)

OffsetNameDescription
7..0MATRIX_SLOT_CYCLE
AT91C_MATRIX_SLOT_CYCLE
Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave when very long burst are used.
17..16MATRIX_DEFMSTR_TYPE
AT91C_MATRIX_DEFMSTR_TYPE
Default Master Type
ValueLabelDescription
0MATRIX_DEFMSTR_TYPE_NO_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR

No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
1MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR

Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
2MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR

Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
19..18MATRIX_FIXED_DEFMSTR4
AT91C_MATRIX_FIXED_DEFMSTR4
Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave
ValueLabelDescription
0MATRIX_FIXED_DEFMSTR4_ARM926I
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I

ARM926EJ-S Instruction Master is Default Master
1MATRIX_FIXED_DEFMSTR4_ARM926D
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D

ARM926EJ-S Data Master is Default Master
2MATRIX_FIXED_DEFMSTR4_HPDC3
AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3

HPDC3 Master is Default Master

MATRIX: AT91_REG MATRIX_PRAS0 PRAS0 (ram0)

MATRIX: AT91_REG MATRIX_PRAS1 PRAS1 (ram1)

MATRIX: AT91_REG MATRIX_PRAS2 PRAS2 (ram2)

MATRIX: AT91_REG MATRIX_PRAS3 PRAS3 (ebi)

MATRIX: AT91_REG MATRIX_PRAS4 PRAS4 (periph)

MATRIX: AT91_REG MATRIX_MRCR Master Remp Control Register

OffsetNameDescription
0MATRIX_RCA926I
AT91C_MATRIX_RCA926I
Remap Command for ARM926EJ-S Instruction Master
0: No Effect
1: This command bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x
1MATRIX_RCA926D
AT91C_MATRIX_RCA926D
Remap Command for ARM926EJ-S Data Master
0: No Effect
1: This command bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x