Reconfigurable Computing: Designflow from VHDL and its application to ASIP

Jonas Folkesson

Supervisors: J. Becker, T. Le

Darmstadt Univ. of Technology

Institute of Microelectronic Systems

Reconfigurable Computing is currently a new and interesting research topic. Using the newest FPGA technology, it allows the user to customize the hardware on-line and/or partially to perform algorithms according to changing environment characteristics. This thesis work concerns the setup, development and implementation of a design flow starting from a VHDL model to a netlist which can be directly mapped on a FPGA. The H.O.T Works PCI Board utilizing Xilinx 6200 FPGAs represent the underlying development platform. To verify the design flow an application from the area of Application Specific Instruction Set Processor (ASIP) will be used. A specific processor architecture which allows reconfiguration of its instruction sets fits nicely into the concept of Reconfigurable Computing and will be considered for implementation. Algorithms running on this processor can either be an ADSL transceiver/receiver or DCT for image processing.